Thermal analysis and model identification techniques for a logic + WIDEIO stacked DRAM test chip

• DOI: 10.5555/2616606.2617079
• Publication Date: 2014-03-24
• Authors: Francesco Beneventi; Andrea Bartolini; Pascal Vivet; Denis Dutoit; Luca Benini
• Keywords: Dram

High temperature is one of the limiting factors and major concerns in 3D-chip integration. In this paper we use a 3D test chip (WIDEIO DRAM on top logic die) equipped with sensors heaters to explore thermal effects. We correlated real measurements power dissipated by using model learning techniques. The resulting compact able predict temperatures at locations far from infer dissipation any location chip. Results are verified mean an off-sample validation technique show high accuracy when compared silicon measurements.