Implementation of a linear histogram BIST for ADCs

• DOI: 10.5555/367072.367829
• Publication Date: 2001-03-13
• Authors: F. Azaı̈s; Serge Bernard; Yves Bertrand; M. Renovell
• Keywords: Built-in self-test

This paper validates a linear histogram BIST scheme for ADC testing. uses time decomposition technique in order to minimize the required hardware circuitry. A practical implementation is described and structure together with operating mode of different modules are detailed. Through this implementation, performances limitations proposed evaluated both terms additional circuitry test time.