Impact of geometrical parameters on the electrical performance of network-channel polycrystalline silicon thin-film transistors

• DOI: 10.7567/jjap.57.104001
• Publication Date: 2018-09-13T10:13:36Z
• Authors: Junyoung Lee; Hojoon Lee; Bo Jin; Hyeongwan Oh; Sangwon Baek; Gilsang Yoon; Yongsu Lee; Rock-Hyun Baek; Jeong-Soo Lee
• Keywords: SEQUENTIAL LATERAL SOLIDIFICATION; MEMORY; DUAL-GATE STRUCTURE; 01 natural sciences; DISPLAYS; REDUCTION; GRAIN-BOUNDARY; MOSFETS; RELIABILITY; 0103 physical sciences; POLYSILICON TFT; SI

The effects of geometrical parameters on the electrical characteristics of network-channel low-temperature polycrystalline silicon (LTPS) thin-film transistors (TFTs) were investigated. The grain boundary and interface trap densities were also extracted using parameters such as hole-to-hole distance, hole-branch top width, effective channel width, and area filling factor (A F). It was found that the electrical characteristics were largely dependent on A F, mainly owing to reduced trap densities. However, excessive hole formation in the network-channel structure was found to increase channel resistance and decrease drain current. These results suggest that, for a given footprint device area, denser hole patterns are preferred for achieving better electrical characteristics in novel network-channel LTPS TFTs.