Hybrid Interconnect Design for Heterogeneous Hardware Accelerators

• DOI: 10.7873/date.2013.178
• Publication Date: 2013-06-25T13:33:01Z
• Authors: Cuong Pham-Quoc; Jan Heisswolf; Stephan Werner; Zaid Al-Ars; Jurgen Becker; Koen Bertels
• Keywords: ddc:004; DATA processing & computer science; 0202 electrical engineering, electronic engineering, information engineering; 02 engineering and technology; info:eu-repo/classification/ddc/004; 004

The communication infrastructure is one of the important components of a multicore system along with the computing cores and memories. A good interconnect design plays a key role in improving the performance of such systems. In this paper, we introduce a hybrid communication infrastructure using both the standard bus and our area-efficient and delay-optimized network on chip for heterogeneous multicore systems, especially hardware accelerator systems. An adaptive data communication-based mapping for reconfigurable hardware accelerators is proposed to obtain a low overhead and latency interconnect. Experimental results show that the proposed communication infrastructure and the adaptive data communication-based mapping achieves a speed-up of 2.4× with respect to a similar system using only a bus as interconnect. Moreover, our proposed system achieves a reduction of energy consumption of 56% compared to the original system.