A5021962931- Semiconductor materials and devices
- Advancements in Semiconductor Devices and Circuit Design
- Integrated Circuits and Semiconductor Failure Analysis
- Advanced Memory and Neural Computing
- Transportation Planning and Optimization
- Urban Planning and Valuation
- Ferroelectric and Negative Capacitance Devices
- Aviation Industry Analysis and Trends
- Transportation and Mobility Innovations
- Urban and Freight Transport Logistics
- Low-power high-performance VLSI design
- Urban Transport and Accessibility
- Carbon Nanotubes in Composites
- Diverse academic and cultural studies
- Traffic and Road Safety
- Nanowire Synthesis and Applications
- Maritime Ports and Logistics
- Silicon Carbide Semiconductor Technologies
- Urban Design and Spatial Analysis
- Advanced Data Storage Technologies
- Quantum and electron transport phenomena
- Graphene research and applications
- Economic and Environmental Valuation
- Electronic and Structural Properties of Oxides
- Urban Planning and Landscape Design
Synopsys (United States)
2022-2024
University of Palermo
2008-2023
Synopsys (Switzerland)
2021
Osys Technology
2017-2020
Gold Standard Simulations (United Kingdom)
2015-2016
University of Glasgow
2012-2015
Tecnologia Energia Ambiente Materiali (Italy)
2004-2014
Politecnico di Milano
2008-2011
IULM University
2010
Consorzio Nazionale Interuniversitario per la Nanoelettronica
2010
The aim of this systematic review was to point out the current state precision beekeeping and draw implications for future studies. Precision is defined as an apiary management strategy based on monitoring individual bee colonies minimize resource consumption maximize productivity. This subject that has met with a growing interest from researchers in recent years because its environmental implications. Preferred Reporting Items Systematic Reviews Meta-Analysis (PRISMA) selected conduct...
In this paper, we use an automated tool flow in a 14 nm CMOS fin-shaped field-effect transistor (FinFET)/ static random access memory (SRAM) simulation-based design-technology cooptimization (DTCO) including both process-induced and intrinsic statistical variabilities. A 22 FinFET technology is used to illustrate the sensitivity fin shape variation motivate paper. Predictive Technology Computer Aided Design (TCAD) simulations have been carried out evaluate performance ahead of silicon....
Advanced Traveller Information Systems (ATISs) include a broad range of advanced computer and communication technologies. These systems are designed to provide transit riders pre-trip real-time information, make better informed decisions regarding their mode travel, planned routes travel times. ATISs in-vehicle displays, terminal or wayside based information centres, by phone mobile internet. In this article, Stated Preference survey has been carried out in order know the preferences public...
This letter presents a numerical investigation of the statistical distribution random telegraph noise (RTN) amplitude in nanoscale MOS devices, focusing on change its main features when moving from subthreshold to on-state conduction regime. Results show that while can be well approximated by an exponential behavior subthreshold, large deviations this appear toward regime, despite low probability tail at high RTN amplitudes being preserved. The average value is shown keep inverse...
We present a detailed semi-analytical investigation of the transient dynamics gate-all-around (GAA) charge-trap memories. To this aim, Poisson equation is solved in cylindrical coordinates, and modification well-known Fowler–Nordheim formula proposed for tunneling through dielectric layers. Analytical results are validated by experimental data on devices with different gate stack compositions, considering quite extended range biases times. Finally, model used parametric analysis GAA cell,...
This article is a review of the state-of-art carbon nanotube interconnects for Silicon application with respect to recent literature. Amongst all research on interconnects, those discussed here cover 1) challenges current copper 2) process & growth compatible back-end-of-line integration, and 3) modeling simulation circuit-level benchmarking performance prediction. The focus evolution from process, theoretical modeling, experimental characterization on-chip interconnect applications. We...
This paper investigates the limitations to accuracy and main issues of spectroscopic analyses random telegraph noise (RTN) traps in nanoscale MOSFETs. First, impact major variability sources affecting decananometer MOSFET performance on both RTN time constants trap depth estimation is studied as a function gate overdrive. Results reveal that atomistic doping metal granularity broaden statistical distribution far more than what comes from position 3-D device electrostatics, contributing,...
This paper presents a thorough numerical investigation of the effect nonuniform doping on random telegraph noise (RTN) in nanoscale Flash memory devices. For fixed average threshold voltage, statistical distribution RTN fluctuation amplitude is studied with nonconstant concentrations length, width, or depth direction channel, showing that increase at active area corners and retrograde <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML"...
We present a dynamic random access memory (DRAM) design technology co-optimization (DTCO) methodology that allows the optimization of DRAM cell structure in presence contact resistance variation, trap-assisted tunneling (TAT) leakage and storage node capacitance variation. showcase our features results by studying metal gate work function under constraints writeability, retention time (tRET) performance, robustness to row hammer effect. Our simulation show performance its reliability are...
This paper presents a physics-based model that is able to describe the TANOS memory programming transients in Fowler-Nordheim uniform tunneling regime across bottom-oxide layer.The carefully takes into consideration trapping/detrapping processes nitride, limited number of traps available for charge storage, and their spatial energetic distribution.Results are good agreement with experimental data on devices different gate-stack compositions, considering quite extended range gate biases...
Pedestrians walk everyday to satisfy their basic necessities.They need an environment that reflects requirements and expectations, in other words "liveable" as much possible.So we should offer tools could allow a complete clear evaluation of the existing walking environment, taking into account both pedestrian urban schemes.To measure mobility performance usually use indicators, which performances grant quick estimation progress.Indicators are universally acknowledged synthetic standard...
In this paper, we have studied the impact of quantum confinement on performance n-type silicon nanowire transistors (NWTs) for application in advanced CMOS technologies. The 3-D drift-diffusion simulations based density gradient approach that has been calibrated with respect to solution Schrödinger equation 2-D cross sections along direction transport are presented. simulated NWTs and dimensional characteristics representative expected at a 7-nm technology. Different gate lengths,...
New transistor architectures such as fully depleted silicon on insulator (FDSoI) MOSFETs and FinFETs have been introduced in advanced CMOS technology generations to boost performance reduce statistical variability (SV). In this paper, the robustness of these random telegraph noise bias temperature instability issues is investigated using comprehensive 3-D numerical simulations, results are compared with those obtained from conventional bulk MOSFETs. Not only impact static trapped charges...
In this paper we illustrate how the predictive Technology Computer Aided Design (TCAD) process device simulation can be used to evaluate process, statistical, and time-dependent variability at early stage of development new technology. This is critically important for delivery accurate Process Kits, including variability, statistical (degradation) their interactions correlations. also critical TCAD-based Design-Technology Co-Optimisation (DTCO). To accomplish task, fast, large area Coventor...
The experimental results from 8 nm diameter silicon nanowire junctionless field-effect transistors with gate lengths of 150 are presented that demonstrate on-currents up to 1.15 mA/μm for 1.0 V and 2.52 1.8 overdrive an off-current set at 100 nA/μm. On- ratios above 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">8</sup> a subthreshold slope 66 mV/dec demonstrated 25 °C. Simulations using drift-diffusion which include density-gradient quantum...
The variability in trap-assisted tunneling leakage that is enhanced by random discrete dopants (RDD) causes refresh failure scaled 6F <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> dynamic random-access memory (DRAM) cells. Thus, the worst-case analysis high demand, but it requires significant computational cost. To overcome this issue, we performed 200 simulations with RDD and a single trap to train multi-layer neural-network (NN)...
This paper presents a comprehensive investigation of statistical effects in deeply scaled nitride memory cells, considering both atomistic substrate doping and the discrete localized nature stored charge layer. By means 3-D TCAD simulations, dispersion threshold voltage shift induced by single electron is evaluated presence non-uniform conduction. The role electrostatics on results highlighted, showing latter as major spread source. more than one then analyzed, that for increasing numbers...
In this paper, by means of simulation, we have studied the implications using channel doping to control threshold voltage and leakage current in bulk silicon FinFETs suitable for 10-nm CMOS technology generation. The level high-performance designed 100-nA/μm has been increased achieve 10 1-nA/μm currents. Ensemble Monte Carlo (EMC) simulations are used estimate impact on transistor performance. Atomistic drift-diffusion calibrated results EMC evaluate random discrete dopants, line edge...
Modeling and simulation is increasingly critical to memory technology exploration development, as relentless scaling demands innovation, pushes the limits of physics, increases risk cost making architectural choices. Examples are given demonstrate value multiscale, multi-physics modeling complex problems, including a) row hammer 4F2 floating body effects in DRAM; b) RTN program noise 3D NAND; c) unit process, integration, wafer warpage; d) Vth engineering at atomic level.
In this paper we present a reliability simulation framework from atomistic simulations up to circuit simulations, including traps interactions with variability sources. Trapping and detrapping dynamics are reproduced by kinetic Monte-Carlo engine, which enables oxide degradation such as BTI RTN phenomenon on large ensembles of devices. Based these results compact models extracted lifetime projections derived.
This paper presents a detailed investigation of charge-trap memory programming by means 3-D TCAD simulations accounting both for the discrete and localized nature traps statistical process ruling granular electron injection from substrate into storage layer. In addition, correct evaluation threshold-voltage dynamics, cell electrostatics drain current are calculated in presence atomistic doping, largely contributing to percolative conduction. Results show that low average efficiency commonly...