Modern day smart grid technology relies heavily on communication networks for two-way between load, generation, transmission, and control centre. As a part of the grid, meters use advanced metering infrastructures (AMI) that are widely distributed interconnected to network. Such integrated infrastructure has made power network easy diagnose control. But unfortunately, this system vulnerable various forms cyber-attacks have caused major concerns researchers in recent times. first step towards...

This paper provides performance evaluations of two state-of-the-art terrestrial broadcasting systems, ATSC 3.0 and 3GPP Rel-17 5G broadcast, in terms physical layer capability, network deployment operating costs. The performances are evaluated the mobile environment, considering practical implementations handheld terminals. Extensive simulation results demonstrate that outperforms because well-designed bit interleaved coded modulation (BICM) time interleaver can mitigate deep signal fades....

"Verification" of large multiprocessor designs currently heavily on simulation. Formal techniques such as model checking are typically only applied to small parts the system, due issues computational and notational complexity. With these two facts in mind authors have designed a platform which aims help bridge gap between formal verification They present temporal logic specification language includes constructs for specifying system behavior at high level abstraction, discuss its use...

Increased usage of video consumption along with a host new services such as software download over wireless networks, group communications, and Internet Things (IoT) applications have created need for support Multicast Broadcast Services (MBS) in networks. While the Third Generation Partnership Project (3GPP) is defining its own mechanism MBS Fifth (5G) system, supplementing native 5G non-3GPP Networks may bring additional advantages. A unique characteristic 3GPP System (5GS) architecture...

Cache-coherent multiprocessors are typically verified by extensive simulation with randomly generated testcases. With this methodology, certain aspects of test coverage can be measured using monitors that record the occurrence specific events during simulation. If do not occur sufficiently often, designer must somehow bias random generator or write hand-written testcases to improve desired event. This is usually a labor-intensive process made worse frequent changes in design specifications...

A blind classification SoC for cognitive radios, featuring multi-signal channelization, 16-core dynamic parallelism-frequency scaling and GALS-based multithreading, is realized in 40nm CMOS. Targeting ≥95% detection probability < 0.5% false-alarm rate, the achieves a throughput-insensitive energy efficiency of 11.9–13.6GOPS/mW multiple 7.8–125MHz bandwidth-agnostic signals 500MHz channel. The shows 2.1× lower energy, >2.7× less variation, 1.2× baseband area up to 4× processing time reduction...

A wideband signal sensor is an essential component to enable cognitive radio and dynamic spectrum access techniques, providing real-time detection modulation classification in a environment of interest. The problem challenging, requiring processing suite incorporating detection, estimation, classification, with stringent power objectives widespread use untethered battery powered devices. This article provides overview integrated system-on-chip extremely low-power solution, including...

We present a fully integrated hybrid filter bank ADC based on an analog-FFT geared for baseband signal processing in wireless receivers. The design consists of 8-point A-FFT analysis bank, VGA and sub-ADC the analog domain, inverse calibration FFT synthesis digital domain. proposed structure enables signals each channel 450MHz wide band system to be separately digitized using full dynamic range ADC. prototype is implemented TSMC's 40nm CMOS GP process. A does not have constant average noise...

This paper presents a simulation-based method for verifying coherency in weakly ordered shared memory multiprocessor systems. methodology requires minimal assumptions regarding the implementation details, such as coherence protocol and cache line replacement rules. Independence from details architectural verification is achieved via technique called data-coloring. The non-determinism arising weak ordering resolved by introducing notion of valid sets checking correctness operations. We...

This paper provides performance evaluations of 5G NR-MBS for terrestrial broadcasting environments. The physical layer is analyzed through theoretical point view and block error rate (BLER) over high-power high-tower (HPHT) infrastructure. Considering the future development services, this focuses on evaluation NR unicast numerology including length cyclic prefix (CP) HPHT single frequency network (SFN) Specifically, it demonstrated that effect CP decoding depends transmission quality channel...

The CEBAF accelerator delivers continuous wave (CW) electron beams to three experimental Halls. In Hall A, all experiments require continuous, non-invasive current measurements and a few an absolute accuracy of 0.2 % in the range from 1 180 /spl mu/A. A Parametric Current Transformer (PCT), manufactured by Bergoz, has accurate stable sensitivity 4 RAN, but its offset drifts at RA level over time preclude direct use for measurements. Two cavity monitors are calibrated against PCT with least...

Today's deep sub-micron semiconductor technology has enabled large-scale integration of multi-million gates consisting reusable intellectual property (IP), on-chip memory and user-defined logic on a single chip. The design such SoC introduced several challenges in terms increased complexity the areas functional verification, timing closure, physical design, signal integrity, reliability, manufacturing test package design. This tutorial discusses methodology that is based successful digital...

A highly-integrated DSL modem for residential gateway applications is described. The chip integrates a C62x based PHY, AFE, line driver and receiver, power management, broadband controller subsystem. 0.13/spl mu/m 5M CMOS process used to implement the 2.3W chip. Supplies are 1.5V digital 3.3V analog subsystems.

The evolution of wireless standards has introduced new challenges for the platforms and compute engines used to implement them. complexity software development is often overlooked as purpose-specific evolve. We investigate in RAN ways this process can benefit from standardization. Arguing that graph models are best way represent signal processing flows, we drive their implementation using current developments O-RAN standards. present how our contributions help achieve a portable physical...

The long development times and high costs of multiprocessor (MP) designs arise from their design complexity. To reduce the time costs, it is critical that bugs are detected early in cycle using verification tools. traditional method hardware to simulate actual designs, usually specified a description language such as VHDL. Two major drawbacks this methodology when applied MP systems huge size models simulation times. In addition difficulty detecting incorrect behavior cache coherent systems,...

This paper introduces a model modification procedure to adapt single-frequency network (SFN) channel models the receiver directivity. The presented work is sequel of [1], extending modeling framework in parametrically adjustable form. Behind this extension, it remarked that fading SFNs can be realized differently if changes antenna beam pattern or orientation. To reflect aspect, proposed method recalculates response gain each signal incidence as dependent on network's geometric layout and...

In the past, hardware design validation has relied primarily on simulation. New techniques such as model checking have been introduced but no objective study investigating advantages provide over simulation made. Simulation is a trace elicited by executing test vector; can be viewed exhaustive Each its own set of and limitations. A platform, "Sherlock", was available wherein one could use properties or specifications expressed CTL-like formulae interchangeably for runs checking. this paper...

SoC designs today comprise IP blocks from different design teams and vendors. Because of differing styles being used on IPs, integrating them verifying is a challenge for teams. One the problems that we have found while way reset or initialisation circuitry implemented. Lack knowledge IPs often cause late in flow when perform gate level simulations with backannotated delays, thus uncovering bug due to either incorrect integration assumed behaviour. Transition relation registers can be...

This paper presents a 100MS/s 9b companding SAR ADC which exploits the statistical properties f broadband multi-carrier signals to reduce dynamic range requirement for ADC. The architecture emulates performance of higher resolution by reducing PAPR signal that single carrier. Additionally, gain-before-sampling results in reduced sampling capacitor size lowers power and area. To verify concept, prototype implemented TSMC's 65nm GP CMOS process consumes 12.27 mW at 100 MS/s while extending...

A half-TEM horn antenna with a ground plane for EMI applications is presented. The designed operation from 0.35 GHz to 1.75 VSWR 3:1. simulated gain 5 dBi at frequencies more than 0.8 and 0 less 0.5 GHz. has simple SMA feed mechanism by the virtue of being thus, wideband balun matching dispensed with. portable dimensions 670 × 530 515.38 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> .

Increase in the consumption of real-time and OTT content over cellular networks has driven need for innovation to provide improved QoE subscribers. This paper describes how terrestrial broadcast technologies can complement each other, considering changing patterns bandwidth consumption. Several architectural concepts based on prior work standardization forums they alleviate problem network loading with incidence traffic are presented. The architectures mechanisms which, leveraging proposed...