Joachim K. Anlauf

ORCID: 0000-0001-5280-8202
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About
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Research Areas
  • Neural Networks and Applications
  • Advanced Memory and Neural Computing
  • Robotic Path Planning Algorithms
  • CCD and CMOS Imaging Sensors
  • Robotics and Sensor-Based Localization
  • Formal Methods in Verification
  • Autonomous Vehicle Technology and Safety
  • Video Surveillance and Tracking Methods
  • Embedded Systems Design Techniques
  • Embedded Systems and FPGA Design
  • Modular Robots and Swarm Intelligence
  • Interconnection Networks and Systems
  • Neural dynamics and brain function
  • Advanced Data Storage Technologies
  • Advanced Vision and Imaging
  • VLSI and FPGA Design Techniques
  • Business Process Modeling and Analysis
  • Physical Unclonable Functions (PUFs) and Hardware Security
  • Fuzzy Logic and Control Systems
  • Image and Signal Denoising Methods
  • Theoretical and Computational Physics
  • Probabilistic and Robust Engineering Design
  • Financial Markets and Investment Strategies
  • Image and Object Detection Techniques
  • Neural Networks and Reservoir Computing

University of Bonn
1999-2019

University of Würzburg
1994

Siemens (Germany)
1993

Justus-Liebig-Universität Gießen
1989-1990

A new learning algorithm for neural networks of spin glass type is proposed. It found to relax exponentially towards the perceptron optimal stability using concept adaptive learning. The patterns can be presented either sequentially or in parallel. prove convergence given and method's performance studied numerically.

10.1209/0295-5075/10/7/014 article EN EPL (Europhysics Letters) 1989-12-01

With the ongoing integration of (dynamic) reconfiguration into current system models, new methodologies and tools are needed to help designer during development process. This article introduces a language extension for SystemC along with design methodology describing simulating dynamically reconfigurable systems at all levels abstraction. The presented library provides maximum freedom description behavior its control, while featuring simulation runtime configuration, removal, exchange custom...

10.1145/1297666.1297681 article EN ACM Transactions on Design Automation of Electronic Systems 2008-01-01

A general purpose neurocomputer, SYNAPSE-1, which exhibits a multiprocessor and memory architecture is presented. It offers wide flexibility with respect to neural algorithms speed-up factor of several orders magnitude — including learning. The computational power provided by 2-dimensional systolic array signal processors. Since the weights are stored outside these NSPs, size processing can be adapted individually application needs. programming language, embedded in C ++ has been defined for...

10.1142/s0129065793000274 article EN International Journal of Neural Systems 1993-12-01

We present a space-efficient, FPGA-optimized architecture to detect collisions among virtual objects. The design consists of two main modules, one for traversing hierarchical acceleration data structure, and intersecting triangles. This paper focuses on the former. is based novel algorithm testing discretely oriented polytopes overlap in 3D space. In addition, we derive new test that can be implemented using fixed-point arithmetic without producing false negatives with bounded error. SystemC...

10.1109/date.2006.243875 article EN 2006-01-01

We present a simulation environment called SPIKELAB which incorporates simulator that is able to simulate large networks of spiking neurons using distributed event driven simulation. Contrary time simulation, usually used neural networks, our needs less computational resources because the low average activity typical networks. The paper addresses speed up an versus and how can be simulated by distribution already available computing resources. It also presents solution for integration...

10.1142/s0129065799000502 article EN International Journal of Neural Systems 1999-10-01

We present a hardware architecture for single-chip acceleration of an efficient hierarchical collision detection algorithm as well simulation results queries using this architecture. The consists two main stages, one traversing simultaneously hierarchy discretely oriented polytopes, and intersecting triangles. Within each stage, the is deeply pipelined parallelized. For first we compare evaluate different traversal schemes bounding volume hierarchies. A in VHDL shows that implementation can...

10.1109/date.2005.167 article EN Design, Automation, and Test in Europe 2005-04-01

10.1209/0295-5075/11/4/016 article EN EPL (Europhysics Letters) 1990-02-15

In this paper we introduce and describe a generic semiconductor-technology independent hardware development environment for class of statistical signal- image processing models. The approach under consideration formally adopts the Bayesian paradigm uses discrete Markov random field (MRF) models to derive joint distribution problems by means mathematically computationally tractable conditional distributions. We experimentally demonstrate prove capabilities respectively concepts proposed...

10.1109/iscas.2004.1328677 article EN 2004-09-07

In this extended abstract we sketch the employment of programmable logic for acceleration simulation pulsed neural networks. We compare our approach to solutions which are based on DSPs and digital neuroprocessors. Our solution is a rapid prototyping accelerator board data flow concept. The provides three module sockets with rather simple 32Bit interface. design focused maximal through-put from each module. Due architecture very high parallelism between modules can be achieved Two devices...

10.1109/fpga.2002.1106683 article EN 2003-06-25

We calculate the direct average ((N)) of number metastable states in projection rule neural network by means saddle-point method. is obtained as a function Hamming distance g to given pattern, stability gamma and energy E. The critical storage capacity model calculated. examination dependence leads lower bounds for energies spin-glass states.

10.1088/0305-4470/27/17/018 article EN Journal of Physics A Mathematical and General 1994-09-07

Software implementations that test two triangles for intersection often favour speed over exact calculation. They leave it to the user choose an or a fast depending on domain of application. Hardware can not opt make this distinction since users will always expect accelerator hardware be applicable in all possible settings. This paper introduces novel approach towards testing triangles. It is based separating axes and lends itself well implementation. To integrable into hierarchical...

10.5220/0001775203550360 article EN cc-by-nc-nd 2009-01-01
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