A5024813896- Radiation Effects in Electronics
- VLSI and Analog Circuit Testing
- Low-power high-performance VLSI design
- Interconnection Networks and Systems
- Embedded Systems Design Techniques
- Parallel Computing and Optimization Techniques
- Semiconductor materials and devices
- Integrated Circuits and Semiconductor Failure Analysis
- Advancements in Semiconductor Devices and Circuit Design
- Distributed systems and fault tolerance
- Physical Unclonable Functions (PUFs) and Hardware Security
- Advanced Memory and Neural Computing
- Software Reliability and Analysis Research
- Real-Time Systems Scheduling
- Reliability and Maintenance Optimization
- VLSI and FPGA Design Techniques
- 3D IC and TSV technologies
- Adversarial Robustness in Machine Learning
- Advancements in Battery Materials
- Spacecraft Design and Technology
- Advanced Neural Network Applications
- Supercapacitor Materials and Fabrication
- Security and Verification in Computing
- Space Technology and Applications
- Graphite, nuclear technology, radiation studies
Universidade Federal do Rio Grande do Sul
2016-2025
University of Rio Grande and Rio Grande Community College
2004-2021
Carnegie Mellon University
2021
Instituto de Información Científica y Tecnológica
2021
Universidade Federal do Rio Grande
2007-2020
Institute of Informatics of the Slovak Academy of Sciences
2020
San Salvatore Hospital
2016
Georgia Institute of Technology
2009
Universidade Estadual do Rio Grande do Sul
2004-2008
Universidade Federal de Santa Catarina
2007
Triple modular redundancy (TMR) is a suitable fault tolerant technique for SRAM-based FPGA. However, one of the main challenges in achieving 100% robustness designs protected by TMR running on programmable platforms to prevent upsets routing from provoking undesirable connections between signals distinct redundant logic parts, which can generate an error output. This paper investigates optimal design (e.g., cleverly inserting voters) ensure robustness. Four different versions digital filter...
FPGAs have become prevalent in critical applications which transient faults can seriously affect the circuit's operation. We present a fault tolerance technique for and permanent SRAM-based FPGAs. This combines duplication with comparison (DWC) concurrent error detection (CEO) to provide highly reliable circuit while maintaining hardware, pin, power overheads far lower than classic triple-modular-redundancy techniques.
Connecting a built-in current sensor in the design bulk of digital system increases sensitivity for detecting transient upsets combinational and sequential logic. SPICE simulations validate this approach show only minor penalties terms area, performance, power consumption
Performance benchmarks have been used over the years to compare different systems. These can be useful for researchers trying determine how changes technology, architecture, or compiler affect system's performance. No such standard exists systems deployed into high radiation environments, making it difficult assess whether in fabrication process, circuitry, software reliability sensitivity. In this paper, we propose a benchmark suite high-reliability that is designed field-programmable gate...
A novel strategy to detect interconnect faults between distinct channels in networks-on-chip is proposed. Short the data, control and communication handshake lines are considered a cost-effective test sequence for Mesh NoC topologies based on XY routing.
The generation and propagation of single event transients (SET) in logic gate chains is studied modeled. Regarding SET generation, we investigate the dependence generated pulse width on struck node capacitance. Rising capacitance may lead to amplified width, indicating that increasing load alone not an option for radiation hardening. also studied, it shown significant broadening or attenuation propagated transient be observed. It chain design (propagation delay high low transitions) has a...
This work discusses the use of two fault-tolerant techniques, duplication with self-checking and triple modular redundancy, for one-hot encoding FSM in SRAM-based techniques. The styles have a significant influence on dependability machine presence bit-flips, known as single event upsets (SEUs). Although style presents best trade-off terms reliability, modern synthesis tools tend to optimize crucial characteristic style. Consequently, techniques must be applied hardware description language...
This paper presents a hybrid technique based on software signatures and hardware module with watchdog decoder characteristics to detect SEU SET faults in microprocessors. These types of have major influence the microprocessor's control-flow, affecting basic blocks transitions between them. In order protect light is implemented spoof data exchanged microprocessor its memory. Since alone not capable detecting errors inside blocks, it enhanced support new then provide full control-flow...
The recent advance of silicon technology has allowed the integration complex systems in a single chip. Nowadays, Field Programmable Gate Array (FPGA) devices are composed not only programmable fabric but also by hard-core processors, dedicated processing block interfaces to various peripherals, on-chip bus structures and analog blocks. Among latest released this type, work focuses 28 nm Xilinx Zynq-7000 All SoC (APSoC). While immune radiation environment space, seems be very attractive for...
Increasing chip power densities allied to the continuous technology shrink is making emerging multiprocessor embedded systems more vulnerable soft errors. Due high cost and design time inherent board-based fault injection approaches, appropriate efficient simulation-based frameworks become crucial guarantee adequate exploration support at early phase. In this scenario, paper proposes a fast flexible injector framework, called OVPSim-FIM, which supports parallel simulation boost up process....
This paper presents a dual-core lockstep (DCLS) implementation to protect hard-core processors against radiation-induced soft errors. The proposed DCLS is applied an Advanced RISC Machine Cortex-A9 embedded processor. Different software optimizations were evaluated assess their impact on performance and fault tolerance. Heavy ions' experiments injection emulation performed analyze the system susceptibility errors performance. Results show that approach able decrease cross section achieve...
All Programmable System-on-Chip (APSoC) devices are designed to provide higher overall system performance and programmable flexibility at lower power consumption costs. Although modern commercial APSoCs offer a plethora of advantages, they prone experience Single Event Upsets. We investigate the impact using different architectures on an APSoC in failure rate. consider memory organization, communication schemes, computing modes. Results show that there several choices resources be chosen...
This article evaluates the RISC-V Rocket processor embedded in a Commercial Off-The-Shelf (COTS) SRAM-based field-programmable gate array (FPGA) under heavy-ions-induced faults and emulation fault injection. We also analyze efficiency of using mitigation techniques based on hardware redundancy scrubbing. Results demonstrated an improvement 3× cross section when scrubbing coarse grain triple modular are used. The presented analogous sensitivity to radiation effects as state-of-the-art soft...
This work is a survey on approximate computing and its impact fault tolerance, especially for safety-critical applications. It presents multitude of approximation methodologies, which are typically applied at software, architecture, circuit level. Those methodologies discussed compared all their possible levels implementations (some techniques more than one level). Approximation also presented as means to provide tolerance high reliability: Traditional error masking techniques, such triple...
This paper presents a detailed evaluation of the efficiency software-only techniques to mitigate SEU and SET in microprocessors. A set well-known rules is presented implemented automatically transform an unprotected program into hardened one. are injected all sensitive areas MIPS-based microprocessor architecture. The each rule combination them tested. Experimental results show inefficiency control-flow detecting majority faults. Three effects non-detected faults explained. conclusions can...
As the technology scales down into deep sub-micron domain, more IP cores are integrated in same die and new communication architectures used to meet performance power constraints. However, technologic advance makes devices interconnects sensitive types of malfunctions failures, such as crosstalk transient faults. This paper proposes fault tolerant techniques protect NoC routers against occurrence soft errors at time, with minimum area overhead. Experimental results show that a cost-effective...