A5087624228- Radio Frequency Integrated Circuit Design
- Advancements in PLL and VCO Technologies
- Microwave Engineering and Waveguides
- Advancements in Semiconductor Devices and Circuit Design
- Analog and Mixed-Signal Circuit Design
- Semiconductor materials and devices
- Semiconductor materials and interfaces
- Superconducting and THz Device Technology
- Electromagnetic Compatibility and Noise Suppression
- Semiconductor Lasers and Optical Devices
University of Padua
2021-2024
This article introduces a 28-nm CMOS digitally controlled oscillator (DCO) based on eight cores, where the number of active cores can be reconfigured to either 2, 4, 6, or 8, trading power consumption for phase noise without incurring an additional penalty. The impact reconfiguration pMOS switches performance is determined through simple yet rigorous time-variant circuit analysis. octa-core DCO covers 27% frequency tuning range between 10.7 and 14.1 GHz with average resolution 6 MHz. A very...
This paper presents an octacore DCO, implemented in a 28 nm CMOS technology, able to achieve outstanding phase noise performance: −126 dBc/Hz at 1 MHz offset from the 10.7 GHz carrier with 173 mW power consumption. The design is scalable, as network coupling oscillator cores can be reconfigured allowing switch off some save without incurring any additional penalty other than one expected reduction of number active cores. DCO achieves 27% tuning range 6 frequency resolution.
Passive resistive mixers find applications in many modern RF and mm-wave circuits, from telecommunications to radar automotive systems. This paper presents an equivalent Thevenin circuit for the analysis of gain bandwidth passive mixer, that takes into account source resistance a finite off-resistance switches. model is applied practical use cases validated against simulations.
The use of a reactive passive mixer is proposed to implement an efficient Cartesian transmitter for IoT applications, capable supporting high-order modulations, and high data rates. Prototypes in 22 nm FD-SOI CMOS technology show 5.5 dBm output-referred 1 dB compression point with 34.1% system efficiency CW operation. Under 2.4 Mbaud, 16-QAM modulation at 2.7 average output power, they achieve 9.6 Mb/s rate, EVM = −24.5 dB, ACLR −32 dBc, P <inf xmlns:mml="http://www.w3.org/1998/Math/MathML"...
The growth of the Internet Things (IoT) is calling for more efficient, higher data rate radios. However, high-order modulations required to push rates, while increasing spectral efficiency, clash with transmitter (TX) power as they require complex and linear systems. An unconventional quadrature modulator, based on reactive passive mixers, proposed key building block simplify signal path a Cartesian TX achieve performance comparable polar architecture enabling use modulation formats. A...