A vertical dielectrically modulated tunnel field-effect transistor (V-DMTFET) as a label-free biosensor has been investigated in this paper for the first time and compared with lateral DMTFET (L-DMTFET) using underlap concept gate work function engineering. To improve performance of (LB), heavily doped front n <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> -pocket gate-to-source overlap is introduced (VB). The integrated effect...

Formation of abrupt tunneling junction for the sub-nanometer tunnel FET (TFET) is crucial achieving better electrical behavior. This task more challenging in case dopingless TFETs (DL TFETs). In this concern, we propose a novel design DL TFET, wherein metallic layer has been placed oxide region at space present between gate and source electrode (used inducing p+ region) conventional n-TFET to overcome issue low on-state current (I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML"...

Steep rise in the subthreshold slope, high current driving capability, and negligible ambipolarity are major prerequisite conditions of tunnel FETs (TFETs) to make it applicable for Analog/RF circuit applications. Along with that, fabrication physically doped TFETs is a concern device technology. In this context, paper deals junctionless TFET metal implanted oxide at source/channel drain/channel junctions enhance its ON-current reduce ambipolar nature. The introduced junction generates...

The manuscript proposes a novel dielectric modulated FET biosensor for the detection of SARS-CoV-2 in terms spike, envelope and DNA proteins virus. models used simulation transfer characteristic proposed sensor both are first calibrated with fabricated sensor. Than modification low workfunction Hf Gate2 (dual metal control gate) has been manuscript. extended provides more space immobilization virus utilize advantages charge plasma formation electrical doping. In manuscript, sensitivity...

A distinct approach is presented for realizing charge plasma tunnel field-effect transistor (CP TFET) wherein p <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> substrate taken as silicon film and then metal electrodes with specific work functions are deposited over the to accumulate n drain intrinsic channel regions. This creates abruptness reduces barrier at source/channel interface of CP TFET, which improves dc characteristics device....

This works shows the effect of different dielectric material which are used in gate metal oxide semiconductor field transistor (MOSFET). Dielectric like silicon dioxide <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(\text{SiO}_{2})$</tex> , nitride xmlns:xlink="http://www.w3.org/1999/xlink">$(\text{Si}_{3}\mathrm{N}_{4})$</tex> hafnium xmlns:xlink="http://www.w3.org/1999/xlink">$(\text{HfO}_{2})$</tex> this study. Changing MOSFETs can reduce...

This work deals with a distinct concept to realise the junction‐less tunnel field effect transistor (JL TFET) by creating plasma of charges. The crux this study is reduce ambipolar conduction and improve high‐frequency figure merits. To construct JL TFET, initially silicon film considered then metal electrodes are used form drain channel region. electrode separated into two sections function section adjacent selected higher than other section. provides non‐uniform doping profile in region...

Circuits for a 1-bit complete adder are proposed in this paper. The suggested circuits have very low power consumption and minimal delay [1]. CMOS technology is used to develop various with delay. Cadence Virtuoso at 90nm implement these, 1.8V supply voltage. [2], delay, area parametric restrictions compared circuit designs, comments made on which design provides the best performance parameter. Power Delay Product indicates circuit's efficiency. Since primary focus of VLSI research design,...

The analog/radio-frequency (RF) performance of a ferroelectric-based substrate metal oxide semiconductor field effect transistor (FE-MOSFET) with dielectric spacer was designed and proposed. utilization gate side wall spacers aims to mitigate short-channel effects (SCEs), improve overall device performance. Simulation results demonstrate enhanced metrics, including improved transconductance (80%), reduced leakage (95.4%), cutoff frequency (25%), making this design promising candidate for...

The charge plasma‐based tunnel field‐effect transistor (TFET) has been seen as the potential candidate to replace conventional TFET it offers fabrication simplicity and its proficiency be used for ultra‐low‐power applications. A plasma (CPTFET) with hetero materials enhancement of device performance is presented. For this, a narrow bandgap material (InAs) instead silicon in source region reducing lateral tunnelling distance at source/channel interface. reduced width junction enables higher...

Recently, the doping-less Tunnel Field Effect Transistor (TFET) has emerged as a novel device for replacement of conventional TFET due to its similar trend in current characteristics and reduced fabrication complexity with low cost. However, impact temperature on performance is yet an undiscovered aspect. The semiconductor devices are known have significant dependence characteristics. Thus, it very much importance analyse behavior at different temperature. In this concern, extensive study...

This paper investigates a comparative analysis of technology computer-aided design (TCAD) versus machine learning (ML) technique for ferroelectric-based substrate metal oxide semiconductor field effect transistor (FE-MOSFET), which shows the low power energy storage device and ML algorithms reduce time or overall process. The simulations carried out through TCAD require approximately 44–46 days, encompassing variations in input parameters like gate work function ([Formula: see text]), doping...

In this work, the authors have focused on increasing current driving capability, speed of operation, suppression parasitic capacitance and ambipolarity charge plasma tunnel field effect transistor (CPTFET). Gate dielectric hetero‐material engineering are employed in CPTFET to obtain better drain current. Introduction high‐k increases injection carriers intrinsic body while a low‐energy bandgap III–V material reduces tunnelling width leading increased rate band‐to‐band electrons thus,...

This article compares the performance of Recessed <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-Source/Drain</inf> Junction less Gate All Around (Re xmlns:xlink="http://www.w3.org/1999/xlink">-S/D-JL-GAA</inf> ) MOSFETs to (JL-GAA) and analyses effects temperature variations on analogue parameters Hot-Carrier Injection (HCI) degradation, additionally a Machine Learning (ML) base technique is introduce find alternative results based TCAD...