A fully integrated WirelessHD compatible 60-GHz transceiver module in 65-nm CMOS process is presented, covering the four standard channels. The silicon die flip-chipped on top of a low-cost HTCC which also includes an external PA and large beamwidth antennas targeting industrial manufacturability. achieves 16QAM OFDM modulation wireless link with 3.8 Gbps over 1 m. consumption 454 mW RX mode (including PLL) 1090 TX PLL PA).

A 53-to-68 GHz power amplifier with an 8-way combiner in standard 65 nm CMOS meets the wireless HDMI standard. Reliability is improved by solving issues of time-dependent dielectric breakdown and hot-carrier-injection degradation. The PA output 18 dBm.

This work shows a complete PLL that is integrated in standard industrial 65nm CMOS technology. frequency synthesizer fully compliant with IEEE 802.15.3c normalization [1–4]. delivers quadrature LO signal around 20GHz and differential 40GHz has 17.9% tuning range. The wide range of permits to cover the full band margin. phase noise −100dBc/Hz at 1MHz offset total power dissipation only 80mW including output buffers amplifiers. Short-range wireless multi-Gb/sec communication systems use...

A 60 GHz wideband power amplifier (PA) is fabricated in a standard CMOS SOI 65 nm process. The PA based on two cascode stages. Input, output and inter-stage matching use coplanar wave guide (CPW) transmission lines that have low losses thanks to the high-resistivity substrate (3 kΩ · cm). measurements are carried out for supply voltages V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> going from 1.2 2.6 achieve saturation of 10 dBm...

This paper presents an original mmW frequency multiplier that provides the channel center frequencies of IEEE 802.15.3c standard from a much lower and fixed 2.16 GHz. It is composed voltage-controlled oscillator (VCO) whose supply periodically switched on-and-off by input signal, providing Periodically Repeated Oscillations Train (PROT). multi-harmonic signal injected into (ILO) locks onto harmonic interest, continuous wave sinusoidal in 60 GHz band. The CMOS 40 nm circuit consumes 32 mW...

A 60-GHz transceiver module fully integrated on silicon interposer technology is demonstrated for the first time. The includes a 65-nm CMOS RFIC and two antennas (transmit, receive) in very compact volume (6.5×6.5×0.6 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> ). fabrication process presented. design measurements of antenna demonstrate good performances with impedance matching over 57-66 GHz band gain up to 5 dBi area. Data...

In this paper, a D-band millimeter-wave low noise amplifier circuit in CMOS SOI 45 nm technology is presented. It achieves 8 dB of figure and 16 gain with 3-dB bandwidth 31.5 GHz (125.5-157 GHz). composed four stages capacitively neutralized differential common-source cells cascaded using integrated mm-wave transformers to achieve high large bandwidth. consumes 75 mW from 1-V voltage supply, occupies compact active area 0.07 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML"...

High-performance integrated slow-wave coplanar waveguides (S-CPW) are compared with conventional (CPW) fabricated in a 65-nm High-Resistivity-SOI (HR-SOI) CMOS technology. As expected, S-CPW demonstrates better performance at millimeter-wave frequencies term of higher effective dielectric permittivity, which is due to the patterned floating shield inserted between transmission line and substrate. In addition, shows lower attenuation constant despite added metallic on HR For demonstration...

This work describes an UWB impulse transmitter with integrated antenna in the 60 GHz band implemented CMOS65nm SOI technology. The aims low-power short-range high data-rate communication systems for fast-downloading applications. It consists of oscillator that is switched on-and-off by digital data to be transmitted and a medium power amplifier. fabricated on two chips: one direct on-chip measurements another implementing antenna. are performed free space both continuous wave operating...

A 60-GHz low power fully integrated transceiver including antennas, fabricated in CMOS 65nm SOI and packaged cost QFN is described. The circuit achieves 2 Gbps 500 Mbps rates at 7.5 cm 22.5 transmission ranges respectively. energy efficiency lower than 50 pJ/bit thanks to scalable consumption using pulse generator Super Regenerator Oscillator architecture.

This paper presents the design of a wideband and high-linearity E -band transmitter integrated in 55-nm SiGe BiCMOS technology. It consists double-balanced bipolar ring mixer which upconverts 16-21-GHz IF signal to 71-76- 81-86-GHz bands by use 55/65-GHz local oscillator signal, followed broadband power amplifier employs 2-way output combining using an low-loss balun transformer. The exhibits average conversion gain 24 dB 22 at bands, respectively, with 1-dB compression point greater than 14...

In this letter, an ultra-broadband D-band wireless front-end transmitter (TX) in 45-nm CMOS SOI is proposed. Based on channel bonding and 64-QAM modulation, it achieves 84.8-Gb/s data rate by combining 8 × 2.16 GHz baseband channels. The eight channels are aggregated at intermediate frequency (IF) two sets of four then upconverted to adjacent sub-bands D-band. required millimeter-wave local oscillators (LOs) generated on-chip. IF band 57.96 66.66 GHz, the considered transmission from 140.895...

This paper presents an energy-efficient wideband D- band wireless link using receiver (RX) and transmitter (TX) modules based on a channel-bonding scheme. The include RX TX integrated circuits (ICs) fabricated in 45nm CMOS RFSOI technology. They are mounted low-cost multi-layer printed circuit boards (PCBs) connected to patch antennas. ICs composed of two down-conversion up-conversion chains, respectively, operating over contiguous sub- bands around 147.96 GHz. required multiple...

A high-data-rate <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$D$ </tex-math></inline-formula> -band transmitter (TX) module cointegrating a dual-channel TX integrated circuit (IC) in 45-nm CMOS partially deplated silicon-on-insulator (PDSOI) technology and an antenna is presented. The proposed system-in-package based on innovative channel-bonding technique fabricated using low-cost printed board...

This paper presents a baseband to D-band wireless link based on transmitter module integrating 45-nm CMOS channel bonding chipset and high-gain antenna in PCB technology. The realized using commercial receiver at 42 cm achieves data rate of 57.6 Gb/s multi-channel 16-QAM with transmitting energy efficiency 27.4 pJ/b.

In this paper, the high-frequency properties of MOSFETs at low-temperature operation are investigated through measurements and electrical simulations. The experimental results show that device achieves a 335-GHz f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> 300-GHz xmlns:xlink="http://www.w3.org/1999/xlink">t</sub> when operating low temperature (78 K), which constitutes, respectively, 78% 34% improvement compared to room...

A hybrid on-chip/in-package integrated antenna is designed and demonstrated for the first time in a QFN (quad flat no lead)-packaged 60-GHz ultra-wide-band (UWB) low-power transceiver. The on-chip radiating element folded dipole realized on transceiver high-resistivity silicon chip (CMOS-SOI technology). It coupled electromagnetically to patch embedded under package lid. design was performed with full 3D EM model of packaged experimental radiation patterns gain values are agreement...

V-band integrated transceiver modules based on a multi-layer organic interposer technology are developed for user terminal and access point applications in future 5G mobile networks with the objective to have an efficient, scalable cost-effective architecture. The main design constraints issues discussed. A 10×10-mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> module, designed user-terminal applications, separate Rx Tx antennas is...

This paper describes a high order programmable frequency multiplier in the 60 GHz band. The circuit implements four chains that can address simultaneously different frequencies of IEEE 802.11ay standard and aims to channel bonding, full duplex, or MIMO systems. It is fabricated 45nm CMOS PDSOI technology. Each chain consumes 32.6mW achieves lower than 178fsec integrated jitter (in band 10KHz-1.08GHz) for all synthesized frequencies.

AC performances of carbon nanotube field-effect transistors (CNT-FETs) are analyzed by means scattering parameters measurements. The active ac properties CNT-FETs clearly demonstrated up to 80 MHz and indications behavior obtained 1 GHz. From these measurements, a small signal equivalent circuit is proposed validated 10 MHz. extraction procedure the determination intrinsic elements pointed out.

A 6.5×6.5 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> compact silicon interposer encompassing 2 Tx/Rx antenna, one RF chips, TSV via-last has been designed and fabricated for 60 GHz fast data transmission applications. First characterizations are described in this paper with a focus on reliability, antenna performances Through-Silicon-Vias (TSV) characterization. It is first shown that more than 500 thermal cycles can be achieved...

A Fully integrated 283 GHz heterodyne receiver in 65 nm CMOS process is presented this paper. The circuit includes a resistive differential mixer, an intermediate frequency amplifier and 282 subharmonic injection locked oscillator. on-chip oscillator generates 94 fundamental tone but exploits third harmonic. An signal of 47 (one sixth the RF frequency) used to lock on reference. measured conversion gain -6 dB for DC power consumption 97.6 mW. Simulated noise figure 38 dB. chip size 820 μm ×...

A low power 278-GHz CMOS zero-IF heterodyne receiver is presented in this paper. The circuit includes a passive mixer, baseband amplifier, triple push sub-harmonic injection locked oscillator and an integrated antenna. measured maximum conversion gain -12 dB the DC consumption 47 mW. on-chip antenna size 390×280 μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . used as THz detector for imaging. It shown that thanks to structure...

We present two high-efficiency baseband (BB)-to- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${D}$ </tex-math></inline-formula> -Band transmitting systems based on a novel channel-aggregation architecture. They comprise first integrated circuit (IC) for channel aggregation at intermediate frequency (IF) and two-channel 45-nm CMOS transmitter (TX) flip-chipped antenna-in-package (AiP), which illuminates...

An empirical nonlinear model for sub-250 nm channel length MOSFET is presented which useful large signal RF circuit simulation. Our made of both analytical drain current and gate charge formulations. The expression continuous infinitely derivable, conservation taken into account, as the capacitances derive from a single expression. model's parameters are first extracted, prior implementation simulator. It validated through dc, ac, measurements compared to