We present a novel testing scheme for TSVs in 3D IC by performing on-chip TSV monitoring before bonding, using sense amplification technique that is commonly seen on DRAM. By virtue of the inherent capacitive characteristics, we can detect faulty with little area overhead circuit under test.

Pre-bond test is preferred for a three-dimensional integrated circuit (3D IC), since it reduces stacking yield loss and thus saves cost. In this paper, we present two schemes testing through-silicon vias (TSVs) by performing on-chip screening before wafer thinning bonding. The first scheme blind TSVs, which have one end floating, using charge-sharing technique commonly seen in DRAM. second open-sleeve shorted to the substrate, voltage-dividing ROM. By virtue of inherent capacitive resistive...

Three-dimensional (3D) integration using through silicon via (TSV) has been widely acknowledged as one future integrated-circuit (IC) technology. A 3D IC including multiple dies connected with TSVs offers many benefits over current 2D ICs. However, the testing of ICs is much more difficult than that In this paper, we propose a cost-effective built-in self-test circuit (BIST) to test IC. The BIST scheme, arranging into arrays similar memory, features low test/diagnosis time and area cost....

In this work, we present a robust small delay test scheme for through-silicon vias (TSVs) in 3D IC. By changing the output inverter's threshold of TSV testable oscillation ring structure, can approximate propagation across that TSV, and thereby detecting fault. SPICE simulation reveals Variable Output Thresholding (VOT) technique is still effective even when there significant process variation slow with some resistive open defect may escape traditional at-speed test.

In this paper, we propose a method that can characterize the propagation delays across Through Silicon Vias (TSVs) in 3D IC. We adopt concept of oscillation test, which two TSVs are connected with some peripheral circuit to form an ring. Upon foundation, technique called sensitivity analysis further derive delay each individual TSV participating ring-a distilling process. process, perturb strength drivers, and then measure their effects terms change ring's period. By following analysis, be...

AbstractÐHoneycomb and diamond networks have been proposed as alternatives to mesh torus architectures for parallel processing.When wraparound links are included in honeycomb networks, the resulting structures can be viewed having derived via a systematic pruning scheme applied of 2D 3D tori, respectively.The removal links, which is performed along diagonal direction, preserves network's node-symmetry diameter, while reducing its implementation complexity VLSI layout area.In this paper, we...

A parametric delay fault could arise in a through-silicon via (TSV) of 3-D IC due to manufacturing defect. Identification such is essential for diagnosis, yield-learning, and/or reliability screening. In this paper, we present an innovative design-for-testability technique called variable output thresholding. We discovered that by dynamically switching the TSV from normal inverter Schmitt-Trigger inverter, on can be characterized and detected. SPICE simulation reveals remains effective even...

In this paper, we propose a method and the required architecture for characterizing propagation delays of through Silicon vias (TSVs) in 3-D IC. First all, every two TSVs are paired up to form an oscillation ring with some peripheral circuits. Their joint performance can thus be measured roughly by period ring. Next, utilize technique called sensitivity analysis further derive delay each individual TSV participating ring-a distilling process. process, perturb strength drivers, then measure...

The three-dimensional (3D) integration technology using through silicon via (TSV) provides many benefits over the 2D technology. Although different manufacturing technologies for 3D integrated circuits (ICs) have been presented, some challenges should be overcome before volume production of ICs. One is testing This paper proposes test interfaces controlling design-for-test in dies a IC. can support pre-bond, known-good stack, and post-bond tests. minimum number required pads proposed...

Three-dimensional integrated circuit (3D IC) has become an emerging technology in view of its advantages packing density and flexibility heterogeneous integration. The multi-core processor (MCP), which is able to deliver equivalent performance with less power consumption, a candidate for 3D implementation. However, when maximizing the throughput MCP, due inherent heat removal limitation, thermal issues must be taken into consideration. Furthermore, since temperature core strongly depends on...

The analog built-in self-test (BIST) scheme, with stimulus generation and response extraction based on the /spl Sigma/-/spl Delta/ modulation, is proven to be quite effective for sampled-data systems. We show that modulators can selected optimally certain applications functional tests. criteria valid tests are also derived. In particular, a frequency test determined by observation range FROR/sub BIST/(z) of BIST circuit. Given transfer function H/sub CUT/(z) circuit under test, requirement...

3-D integration provides a means to overcome the difficulties in design and manufacturing of system-on-chip (SOC) memory products. Introducing short vertical interconnect, called through-silicon via (TSV), makes it feasible repair recycle bad dies by stacking. We propose method accomplish this using dual-TSV hardwired switch (DTHS) which via-hole location is programmable. With DTHS, we activate spare establish inter-die routing. The nothing but good part another die. To be reparable,...

3-D many-core processor (3-D MCP) has become an emerging technology to tackle the power wall problem due rapidly increasing number of transistors. However, when maximizing throughput MCP, which is expressed as a weighted sum speeds, inherent heat removal limitation, thermal issues must be taken into consideration. Since temperature core strongly depends on its location in IC, proper task allocation can alleviate and improve throughput. Nevertheless, conventional techniques require...

With the shrinking of technology node, data retention time DRAM (DRAM) cells is widespread. Thus, number with faults increased. In this paper, therefore, we propose a built-in self-repair (BISR) scheme for DRAMs using redundancies physical and logical reconfiguration mechanisms. Spare rows columns mechanism are used to repair functional caused by defects. bits replace process variation. Also, diagnosis algorithm proposed identify faults. Simulation results show that BISR 2 spare rows,...

This paper describes a four-layer-stacked chip with 45-nm dynamic random access memory (DRAM) dice and 65-nm logic controller, which are interconnected by backside-via-last through-silicon via (TSV) processes. Fabrication of process multiple die stacking using chip-to-chip bonding presented electrical connection between TSV (5-μm-diameter/50-μm-length) Cu interconnects. Excellent fabrication stacked verified that the micro bumps 12-μm diameter bonded three step temperature profile. Further...

In this paper, we discuss a design-for-test technique for the detection of cell stability in static random access memory (SRAM). The power supply to array is isolated and independently accessible from an external terminal. By lowering voltage, degraded, making defective cells susceptible noises induced by read/write operations. On-silicon characterization result using 0.18 /spl mu/m CMOS technology reported. It shows that weak tailing bits statistical distribution can manifest themselves....

Data retention time distribution of a dynamic random access memory (DRAM) has heavy impact on its yield, power, and performance. Accurate detailed information data thus is very important for the DRAM designer user. This paper proposes an FPGA-based test platform analyzing DRAM. Based platform, flow also proposed to classify cells with different times respect supply voltage temperature. We have demonstrated using Micron 2Gb

Power integrity is generally considered to be one of the major bottlenecks hindering prevalence three-dimensional integrated circuits (3D ICs). The higher integration density and smaller footprint result in significantly increased power density, which threatens system reliability. In view this, there has been groundswell interest academia model, design or optimize delivery networks (PDNs) 3D ICs. Unfortunately, while several PDN benchmarks exist for 2D PDNs, none available context 3D. As a...

PDN evaluation/synthesis techniques have been used to facilitate the planning/construction of PDNs in integrated circuits at early physical implementation stages. They are rarely relevant after routing stage when few resources left and hence call for a repair strategy. The reason is that traditional methods often apply wire widening or density increment directly without taking signal into account. Moreover, intuitively adding connections using entire space available quite time-consuming...

Chordal rings have been proposed in the past as networks that combine simple routing framework of with lower diameter, wider bisection, and higher resilience other architectures. Virtually all chordal ring are node-symmetric, i.e., nodes same in/out degree interconnection pattern. Unfortunately, such regular not scalable. In this paper, periodically (PRC) a compromise for combining low node small diameter. By varying PRC parameters, one can obtain architectures significantly different...

IR-drop monitoring has been an effective means to assess the power integrity in real silicon. Existing methods, however, fail achieve a high accuracy and sampling rate simultaneously. In this paper, we present novel method resolve dilemma. First of all, focus on measurement worst-case IR-drop, instead entire sampled VDD waveform. This strategy can make easily viable. Secondly, perform periodic calibration account for not only process variation but also temperature change. Post-layout...

We present a strategy for designing stable insertion sorters based on linear arrays with data-driven control. The novelty of our approach lies in each data item carrying control tag to specify how it is be operated upon by receiving cell and performing two parallel comparisons within cell. To assure first-in/first-out handling equal key values, some items must marked reflect their past histories. Such marking conveniently carried out modifying the item's tag. It combination above features...

As we adopt more advanced process technologies, the volume production of memory devices, such as DRAM and Flash, becomes difficult. It seems inevitable that during ramp-up period, initial manufacturing yield will be lower, it takes time effort to improve a reasonable level. Although redundancy can used eventually, reserved spares may not enough at beginning, so most dies irreparable. We propose usage three-dimensional (3D) integration achieve enhancement. Through silicon vias (TSVs) patch...

A three-dimensional (3D) CMOS imager constructed by stacking a pixel array of backside illuminated sensors, an analog-to-digital converter (ADC) array, and image signal processor (ISP) using micro-bumps (μbumps) through-silicon vias (TSVs) is promising for high throughput applications. However, due to the direct mapping from pixels ISPs, overall yield relies heavily on correctness μbumps, ADCs TSVs -- single defect leads information loss tile pixels. This paper presents error tolerance...

This paper presents a novel die-to-die clock synchronization method that is independent of the inter-die wire delay. Through 2-Phase All-Digital Delay Locked Loop (2P-DLL) and Dual Locking Mechanism (DLM), this can be used to maintain global signal between two dies in 3-D IC, thereby enabling synchronous IC design methodology. Unlike previous designs, ours does not need replicate delay wire. property make our scheme more adaptive various technologies robust PVT variation. Such has several...