Approximate computing is an attractive design methodology to achieve low power, high performance (low delay) and reduced circuit complexity by relaxing the requirement of accuracy. In this paper, approximate Booth multipliers are designed based on radix-4 modified encoding (MBE) algorithms a regular partial product array that employs Wallace tree. Two encoders proposed analyzed for error-tolerant computing. The error characteristics with respect so-called approximation factor related inexact...

Computing systems are conventionally designed to operate as accurately possible. However, this trend faces severe technology challenges, such power consumption, circuit reliability, and high performance. For nearly half a century, performance consumption of computing have been consistently improved by relying mostly on scaling. As per Dennard's scaling, the size transistor has considerably shrunk supply voltage reduced over years, that circuits at higher frequencies but same dissipation...

Machine learning has been pervasively used in a wide range of applications due to its technical breakthroughs recent years. It demonstrated significant success dealing with various complex problems, and shows capabilities close humans or even beyond humans. However, studies show that machine models are vulnerable attacks, which will compromise the security themselves application systems. Moreover, such attacks stealthy unexplained nature deep models. In this survey, we systematically analyze...

In this paper, the designs of both non-iterative and iterative approximate logarithmic multipliers (ALMs) are studied to further reduce power consumption improve performance. Non-iterative ALMs, that use three inexact mantissa adders, presented. The proposed ALMs (IALMs) a set-one adder in adders during an iteration; they also lower-part-or mirror for final addition. Error analysis simulation results provided; it is found LMs with appropriate number bits achieve higher accuracy lower than...

Lattice-based cryptography (LBC) is one of the most promising classes post-quantum (PQC) that being considered for standardization. This brief proposes an optimized schoolbook polynomial multiplication (SPM) compact LBC. We exploit symmetric nature Gaussian noise bit reduction. Additionally, a single field-programmable gate array (FPGA) DSP block used two parallel operations per clock cycle. These optimizations enable significant 2.2× speedup along with reduced resources dimension n = 256....

As technology scaling is reaching its limits, new approaches have been proposed for computional efficiency. Approximate computing a promising technique high performance and low power circuits as used in error-tolerant applications. Among approximate circuits, arithmetic designs attracted significant research interest. In this paper, the design of redundant binary (RB) multipliers studied. Two Booth encoders two RB 4:2 compressors based on (full half) adders are multipliers. The RB-Normal...

Quantum-dot cellular automata (QCA) technology is expected to offer fast computation performance, high density, and low power consumption. Thus, researchers believe that QCA may be an attractive alternative CMOS for future digital designs. Side channel attacks, such as analysis have become a significant threat the security of cryptographic circuits. A attack can reveal secret key from measurements consumption during encryption decryption process. As there no electric current flow in...

As a promising alternative to CMOS technology, QCA circuit design has been extensively studied in recent years. However, although concrete set of rules exist for integrated design, little attention paid the necessary efficient design. This paper compiles important which include layout rules, timing and some special technology ensure circuits function correctly reliably. These will promote development practical systems. A GF(2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML"...

As a new paradigm for nanoscale technologies, approximate computing deals with error tolerance in the computational process to improve performance and reduce power consumption. Majority logic (ML) is applicable many emerging nanotechnologies; its basic building block (the 3-input majority voter, MV) has been extensively used digital circuit design. In this paper, designs of adders multipliers based on ML are proposed; proposed utilize compressors reduction circuitry so-called complement...

Radix-4 Booth encoding provides ease in the generation of partial products, thus is widely used to achieve power-efficient and low-area signed multipliers. Conversely, radix-8 exhibits low-performance as it requires odd multiples multiplicand. In this brief, issue addressed by approximating their nearest power two such that errors complement each other. pursuit an accuracy-energy trade-off, hybrid low radix (HLR) based approximate multipliers (HLR-BM1 HLR-BM2) are designed. HLR-BM2, compared...

This paper proposes several approximate divider designs; two different levels of approximation (cell and array levels) are investigated for non-restoring division. Three subtractor cells proposed designed the basic subtraction; these mitigate accuracy in subtraction with other metrics, such as circuit complexity power dissipation. At level, by considering exact cells, both replacement truncation schemes introduced design. A comprehensive evaluation at cell level is pursued. Different metrics...

This paper proposes several designs of approximate restoring dividers; two different levels approximation (cell and array levels) are employed. Three subtractor cells utilized for integer subtraction as basic step division; these tend to mitigate accuracy in with other metrics, such circuit complexity power dissipation. At level, exact either replaced or truncated the divider designs. A comprehensive evaluation at both cell- (divider) is pursued using error analysis HSPICE simulation;...

This paper presents different approximate designs for computing the FFT. The tradeoff between accuracy and performance is achieved by adjusting word length in each computational stage. Two algorithms modification under a specific error margin are proposed. first algorithm targets an FFT area-limited design compared to conventional fixed design; second so it achieves higher operating frequency. Both of proposed show that efficient balance hardware utilization possible at stage-level....

Convolutional neural networks (CNNs) have been widely used in image classification and recognition due to their effectiveness; however, CNNs use a large volume of weight data that is difficult store on-chip memory embedded designs. Pruning can compress the CNN model at small accuracy loss; pruned operates slower when implemented on parallel architecture. In this paper, hardware-oriented compression strategy proposed; deep network (DNN) divided into "no-pruning layers ( <inline-formula...

The focus of existing designs on approximate radix-8 Booth multipliers has been ASIC-based platforms. These are based an approximation as defined for systems, so they cannot achieve comparable performance gains when used FPGA-based hardware accelerators. This is due to the inherited architectural differences between FPGAs and ASICs. brief bridges this gap by proposing high-performance whose target systems. Hence, two (referred AxBM1 AxBM2) proposed. Approximation implemented such that...

Lattice-based cryptography (LBC) has emerged as the most viable substitutes to classical cryptographic schemes 5 out of 7 finalist in 3rd round NIST post-quantum (PQC) standardization process are lattice based construction. This work explores novel architectural optimizations FPGA-based hardware implementation polynomial multiplication, which is a bottleneck every LBC To target ultra-high throughput, both schoolbook multiplication (SPM) and number theoretic transform (NTT) explored:...

Approximate or inexact computing has recently attracted considerable attention due to its potential advantages with respect high performance and low power consumption. This paper presents the design of an approximate multiplier; this multiplier consists Booth encoder, 4-2 compressor tree structure. The is implemented verified for 8×8, 16×16 32×32-bit signed multiplication schemes targeting applications in embedded systems. Simulation results at 45 nm technology are provided discussed....

Current approaches for building physical unclonable function (PUF) designs resistant to machine learning attacks often suffer from large resource overhead and are typically difficult implement on field programmable gate arrays (FPGAs). In this paper we propose a new arbiter-based multi-PUF (MPUF) design that utilises Weak PUF obfuscate the challenges Strong is harder model than conventional arbiter using attacks. The proposed shows greater resistance attacks, which have been successfully...

With the rapid development of Internet Things (IoT), security has attracted considerable interest. Conventional solutions that have been proposed for based on classical cryptography cannot be applied to IoT nodes as they are typically resource-constrained. A physical unclonable function (PUF) is a hardware-based primitive and can used generate key online or uniquely identify an integrated circuit (IC) by extracting its internal random differences using so-called challenge-response pairs...

A PUF is a physical security primitive that allows to extract intrinsic digital identifiers from electronic devices. It promising candidate improve in lightweight devices targeted at IoT applications due its low cost nature. The Arbiter or APUF has been widely studied the technical literature. However it often suffers disadvantages such as poor uniqueness and reliability, particularly when implemented on FPGAs layout restrictions. To address these problems, new design known FF-APUF proposed;...

The physical unclonable function (PUF) produces die-unique responses and is regarded as an emerging security primitive that can be used for authentication of devices. complexity a conventional PUF design based on ring oscillator (RO) rather high, so limiting its use in many applications. configurable (CRO) has been advocated possible solution to this issue. In paper, low hardware CRO with enhanced capability generate large number bit proposed; only inverter multiplexer are each delay unit....

Silicon physical unclonable function (PUF) has emerged as a promising spoof-proof solution for low-cost device authentication. Due to practical constraints in preventing phishing through public network or insecure communication channels, simple PUF-based authentication protocol with unrestricted queries and transparent responses is vulnerable modeling replay attacks. In this article, we present attack resistant mutual scheme mitigate the limitations applications where resource-rich server...

Approximate recursive multipliers exhibit low-power operation because they are designed using smaller power-efficient approximate multiplier blocks. These building blocks can be configured by varying the approximation levels for a wide range of larger sizes. However, most proposed either slightly inaccurate or hardware-efficient with limited accuracy. In this brief, hybrid partial product-based considering probability distribution input operands. An efficient hardware implementation 4×4 is...

Deep neural networks (DNNs) have been widely used in classification due to their high accuracy. The softmax function is one of the important non-linear functions DNNs. Therefore, performance and efficient hardware design are sought. However, improvement difficult because exponent division units complex. In this paper, we propose new approximate architectures for both units. Compared with state-of-the-art designs, proposed consumes significantly less resources also achieves while maintaining a very