This paper discusses an open source, variation aware Process Design Kit (PDK), based on Scalable CMOS design rules, down to 45nm, for use in VLSI research, education and small businesses. kit includes all the necessary layout rules extraction command decks capture dependent systematic perform statistical circuit analysis. The also a standard cell pad library with support files enable full chip place route verification System Chip designs. Test chips designed this PDK are such way so that...

Computer systems research is often inhibited by the availability of memory designs. Existing Process Design Kits (PDKs) frequently lack compilers, while expensive commercial solutions only provide models with immutable cells, limited configurations, and restrictive licenses. Manually creating memories can be time consuming tedious designs are usually inflexible. This paper introduces OpenRAM, an open-source compiler, that provides a platform for generation, characterization, verification...

This paper presents a high-speed method for function approximation that employs symmetric bipartite tables. performs two parallel table lookups to obtain carry-save (borrow-save) approximation, which is either converted two's complement number or Booth encoded. Compared previous methods approximations, this uses less memory by taking advantage of symmetry and leading zeros in one the It also has closed-form solution entries, provides tight bounds on maximum absolute error, can be applied...

The paper presents a methodology for designing bipartite tables accurate function approximation. Bipartite use two parallel table lookups to obtain carry-save (borrow-save) A carry propagate adder can then convert this approximation two's complement number or the be directly Booth encoded. Our method tables, called Symmetric Table Method, utilizes symmetry in entries reduce overall memory requirements. It has several advantages over previous methods that it: (1) provides closed form solution...

Reducing the power dissipation of parallel multipliers is important in design digital signal processing systems. In many these systems, products are rounded to avoid growth word size. The and area can be significantly reduced by a technique known as truncated multiplication. With this technique, least significant columns multiplication matrix not used. Instead, carries generated estimated. This estimate added with most produce product. paper presents implementation multipliers. Simulations...

A system on chip (SoC) library for MOSIS scalable CMOS rules has been developed It is intended use with Synopsys and Cadence Design Systems electronic design automation tools. Students can also layout tools semi-custom designs insert them the proposed flow. Scalable submicron are used cell library, allowing it to be several AMI TSMC technologies. Consequently, possible fabricate student projects as well do research in through educational program. All steps flow fully automated scripts have...

Truncated multiplication can be used to significantly reduce the power dissipation for applications that do not require correctly-rounded results. This paper presents an efficient method truncated called hybrid-correction truncation utilizes advantages of two previous methods obtain lower average and maximum absolute error. Comparisons are presented contrasting power, area, delay all three compared standard parallel multipliers. Estimates indicate hybrid multipliers dissipate slightly less...

A voltage-scalable SRAM architecture suitable for video applications where energy can be traded with output signal quality is presented. The proposed 6T uses three supply voltages to improve the static noise margin during read and write modes also reduces leakage current in retention mode, hence, it allows aggressive voltage scaling low power multimedia applications. Simulation results IBM/Global Foundries cmos32soi 32-nm CMOS technology show a 69% saving 63% improvement image array compared...

This tutorial paper reviews the state of knowledge on-chip ESD (electrostatic discharging) protection circuit design for integrated circuits. The discussion covers critical issues in design, i.e. test models, failure mechanisms, structures, device modeling, simulation, layout issues, and ESD-to-circuit interactions, etc. review serves to provide practical IC designers with a thorough heady reference dealing complex

This paper presents the design of a combined two's complement and IEEE 754-compliant floating-point comparator. Unlike previous designs, this comparator incorporates both operand types into one unit, while still maintaining low area high speed. The uses novel magnitude with logarithmic delay, plus additional logic to handle floating point operands. fully supports 32-bit 64-bit comparisons, as defined in 754 standard, well comparisons. Area delay estimates are presented for designs...

A standard-cell library for MOSIS scaleable CMOS rules has been developed. It is intended use with Synopsys Design Compiler, Cadence Silicon Ensemble, and Virtuoso or Magic. The targeted the AMI 0.5 /spl mu/m process, which currently offers smallest feature size in educational program. also includes I/O pad cells fully places routes a padframe if desired. All steps design flow are automated only three scripts have tested successfully large VLSI class at Illinois Institute of Technology. To...

Decimal multiplication has grown in interest due to the recent announcement of new IEEE 754R standards and availability high-speed decimal computation hardware. Prior research enabled partial products be coded more efficiently for their use radix 10 architectures. This paper clarifies previous techniques product reduction using carry-save adders presents a 4:2 compressor structure. structure improves performance at expense gates, however, regularity is introduced into circuit promote...

This paper discusses an extension to open source, variation aware process design kit (PDK), based on scalable CMOS rules. PDK is designed for 45 nm feature sizes and utilized use in VLSI research, computer architecture, education small businesses. includes all the necessary layout rules extraction command decks capture dependent systematic perform statistical circuit analysis. The also a standard cell library, MIPSreg processor associated GNU-compliant compiler support files enable full chip...

In this paper, a novel differential single-port 12T SRAM bitcell is presented. This uses read buffer to eliminate disturbance, improves the stability and achieves static noise margin equal its hold margin. Using column-based select signal provides half-select free feature, facilitating bit-interleaving structure reduce multi-bit soft errors by conventional error correcting code techniques. By boosting wordline voltage, can write with no at 300 mV while data be held down 250 in standby mode....

This paper discusses modifications to algorithms compute parallel squaring. The method described in this improves upon designs previously presented utilizing Boolean simplifications. discussed significantly saves area and delay for squarers ranging from 8 bits 32 bits. Results are shown area, delay, power using Virtex 5 Xilinx FPGAs.

This paper presents a method for designing linear, quadratic and cubic interpolators that compute elementary functions using truncated multipliers, squarers cubers. Initial coefficient values are obtained Chebyshev series approximation. A direct search algorithm is then used to optimize the quantized meet user-specified error constraint. The minimizes lengths reduce lookup table requirements, maximizes number of columns area, delay power arithmetic units, maximum absolute interpolator...

Interval arithmetic provides an efficient method for monitoring and controlling errors in numerical calculations. However, existing software packages interval are often too slow numerically intensive computations. This paper presents the design of a multiplier that performs either or floating point multiplication. requires only slightly more area delay than conventional multiplier, is one to two orders magnitude faster implementations

The role of addition and subtraction in digital systems is sometimes complicated due to the arrival certain operands occurring at different times. For example, floating-point arithmetic typically requires exponent logic wait until an output received from post-normalization. Previously, designers have resorted use conditional sum carry-select adders make their design efficient. Recently, a new technique has been proposed that utilizes concept flagged prefix addition. Flagged parallel-prefix...

Parallel-prefix adders draw significant amounts of attention within general-purpose and application-specific architectures because their logarithmic delay efficient implementation in VLSI. This paper proposes a scheme to enhance parallel-prefix for modulo 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</sup> - 1 addition by incorporating Ling equations into structures. As opposed previous research, this work clarifies the use Modulo provides...

Standard cell kits are necessary for modern VLSI implementations. SoCs that must operate in heavy radiation environments take special precautions and implement hardening techniques to produce reliable can high environments. In this paper we describe a methodology the design of hardened library using Radiation Hardened by Design present our results.