GPGPUs have recently emerged as powerful vehicles for general-purpose high-performance computing. Although a new Compute Unified Device Architecture (CUDA) programming model from NVIDIA offers improved programmability general computing, is still complex and error-prone. This paper presents compiler framework automatic source-to-source translation of standard OpenMP applications into CUDA-based GPGPU applications. The goal this to further improve make existing amenable execution on GPGPUs. In...

General-Purpose Graphics Processing Units (GPGPUs) are promising parallel platforms for high performance computing. The CUDA (Compute Unified Device Architecture) programming model provides improved programmability general computing on GPGPUs. However, its unique execution and memory still pose significant challenges developers of efficient GPGPU code. This paper proposes a new interface, called OpenMPC, which builds OpenMP to provide an abstraction the complex offers high-level controls...

The Cetus tool provides an infrastructure for research on multicore compiler optimizations that emphasizes automatic parallelization. infrastructure, which targets C programs, supports source-to-source transformations, is user-oriented and easy to handle, the most important parallelization passes as well underlying enabling techniques.

GPGPUs have recently emerged as powerful vehicles for general-purpose high-performance computing. Although a new Compute Unified Device Architecture (CUDA) programming model from NVIDIA offers improved programmability general computing, is still complex and error-prone. This paper presents compiler framework automatic source-to-source translation of standard OpenMP applications into CUDA-based GPGPU applications. The goal this to further improve make existing amenable execution on GPGPUs. In...

Flexible, accurate performance predictions offer numerous benefits such as gaining insight into and optimizing applications architectures. However, the development evaluation of has been a major research challenge, due to architectural complexities. To address this we have designed implemented prototype system, named COMPASS, for automated model generation prediction. COMPASS generates structured from target application's source code using static analysis, then, it evaluates various...

This paper presents Open Accelerator Research Compiler (OpenARC): an open-source framework that supports the full feature set of OpenACC V1.0 and performs source-to-source transformations, targeting heterogeneous devices, such as NVIDIA GPUs. Combined with its high-level, extensible Intermediate Representation (IR) rich semantic annotations, OpenARC serves a powerful research vehicle for prototyping optimization, instrumentation debugging, performance analysis, autotuning. In fact, is...

Graphics Processing Unit (GPU)-based parallel computer architectures have shown increased popularity as a building block for high performance computing, and possibly future Exascale computing. However, their programming complexity remains major hurdle widespread adoption. To provide better abstractions GPU architectures, researchers vendors proposed several directive-based models. These models different levels of abstraction, required effort to port optimize applications. Understanding these...

This paper presents a directive-based, high-level programming framework for high-performance reconfigurable computing. It takes standard, portable OpenACC C program as input and generates hardware configuration file execution on FPGAs. We implemented this prototype system using our open-source OpenARC compiler, it performs source-to-source translation optimization of the into an OpenCL code, which is further compiled FPGA by backend Altera Offline compiler. Internally, design uses...

With the rise of general purpose computing on graphics processing units (GPGPU), influence from consumer markets can now be seen across spectrum computer architectures. In fact, many high-ranking Top500 HPC systems include these accelerators. Traditionally, GPUs have connected to CPU via PCIe bus, which has proved a significant bottleneck for scalable scientific applications. Now, trend toward tighter integration between and GPU removed this unified memory hierarchy both cores. We examine...

Heterogeneous computing with accelerators is growing in importance high performance (HPC). Recently, application datasets have expanded beyond the memory capacity of these accelerators, and often their hosts. Meanwhile, nonvolatile (NVM) storage has emerged as a pervasive component HPC systems because NVM provides massive amounts at affordable cost. Currently, for accelerator applications to use NVM, they must manually orchestrate data movement across multiple memories this approach only...

Across embedded, mobile, enterprise, and high performance computing systems, computer architectures are becoming more heterogeneous complex. This complexity is causing a crisis in programming systems portability. Several working to address these challenges, but the increasing architectural diversity forcing software stacks applications be specialized for each architecture. As we show, all of approaches critically depend on their runtime system discovery, execution, scheduling, data...

Graphics Processing Unit (GPU)-based parallel computer architectures have shown increased popularity as a building block for high performance computing, and possibly future Exascale computing. However, their programming complexity remains major hurdle widespread adoption. To provide better abstractions GPU architectures, researchers vendors proposed several directive-based models. These models different levels of abstraction, required effort to port optimize applications. Understanding these...

This paper introduces PapyrusKV, a parallel embedded key-value store (KVS) for distributed high-performance computing (HPC) architectures that offer potentially massive pools of nonvolatile memory (NVM). PapyrusKV stores keys with their values in arbitrary byte arrays across multiple NVMs system. provides standard KVS operations such as put, get, and delete. More importantly, advanced features HPC dynamic consistency control, zero-copy workflow, asynchronous checkpoint/restart. Beyond...

OpenACC was launched in 2010 as a portable programming model for heterogeneous accelerators. Although various implementations already exist, no extensible, open-source, production-quality compiler support is available to the community. This deficiency poses serious risk HPC application developers targeting GPUs and other accelerators, it limits experimentation progress specification. To address this deficiency, Clacc recent effort funded by US Exascale Computing Project develop production...

Computer architecture experts expect that non-volatile memory (NVM) hierarchies will play a more significant role in future systems including mobile, enterprise, and HPC architectures. With this expectation mind, we present NVL-C: novel programming system facilitates the efficient correct of NVM main systems. The NVL-C abstraction extends C with small set intuitive language features target memory, can be combined directly traditional model for DRAM. We have designed these new to enable...

GPU performance of the lattice Boltzmann method (LBM) depends heavily on memory access patterns. When LBM is advanced with GPUs complex computational domains, geometric data typically accessed indirectly, and lexicographically in Structure Array (SoA) layout. Although there are a variety existing patterns beyond typical choices, no study has yet examined relative efficacy between them. Here, we compare suite schemes via empirical testing modeling. We find strong evidence that semi-direct...

Fine-grained cycle sharing (FGCS) systems aim at utilizing the large amount of computational resources available on Internet. In FGCS, host computers allow guest jobs to utilize CPU cycles if do not significantly impact local users a host. A characteristic such is that they are generally provided voluntarily and their availability fluctuates highly. Guest may fail because unexpected resource unavailability. To provide fault tolerance without adding significant overhead, it requires predict...

Sparse matrix-vector (SpMV) multiplication is a widely used kernel in scientific applications. In these applications, the SpMV usually deeply nested within multiple loops and thus executed large number of times. We have observed that there can be significant performance variability, due to irregular memory access patterns. Static optimizations are difficult because patterns may known only at runtime. this paper, we propose adaptive runtime tuning mechanisms improve parallel on distributed...