Charge storage characteristics have been investigated in metal-oxide-semiconductor memory structures based on silicon nanocrystals, where various interface traps and defects were introduced by thermal annealing treatment. The observations demonstrate that strong influence the charge behavior, which at internal/surface of nanocrystals states SiO2/Si substrate play different roles, respectively. It is suggested injected charges are mainly stored deep instead conduction band long-term retention...

The quantum mechanical effects in silicon single-electron transistors have been investigated. devices fabricated the form of point contact metal–oxide–semiconductor field-effect with various channel widths using electron beam lithography and anisotropic etching technique on silicon-on-insulator substrates. device an extremely narrow shows Coulomb blockade oscillations at room temperature. At low temperatures, negative differential conductances fine structures are superposed characteristics,...

We have developed a very controllable fabrication process of an extremely narrow (∼10 nm) quantum wire metal-oxide-semiconductor field-effect transistor (MOSFET) on separation-by-implanted-oxygen (SIMOX) substrate using anisotropic etching and selective oxidation technique. The drain current versus gate voltage characteristics show oscillations caused by Coulomb blockade even at room temperature. split into several sharp peaks when the temperature is decreased, indicating that channel...

Random threshold voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">M</sub> ) fluctuation data obtained from multiple fabs, generations and technologies, as well theoretical / TCAD results are carefully compared using a special normalization method. It is revealed that P-FET can be almost fully accounted for by dopant regardless of device designs, whereas extra mechanism(s) significantly contributes to N-FETs.

Internet-of-Things (IoT) technologies require a new energy-efficient transistor which operates at ultralow voltage and power for sensor node devices employing energy-harvesting techniques as supply. In this paper, practical device design guideline low operation of steep-slope negative-capacitance field-effect-transistors (NCFETs) operating sub-0.2V supply is investigated regarding speed, material requirement energy efficiency in the case ferroelectric HfO2 gate insulator, fully compatible to...

We have proposed and investigated a super steep subthreshold slope transistor by introducing negative capacitance of ferroelectric HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> gate insulator to vertical tunnel FET for energy efficient computing. The channel structure are systematically designed maximize the I xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> /I xmlns:xlink="http://www.w3.org/1999/xlink">off</sub> ratio....

We have investigated device design of HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> -based ferroelectric tunnel junction (FTJ) memory. Asymmetry dielectric screening property in top and bottom electrodes is the key for high tunneling electroresistance (TER) ratio. Thus, metal semiconductor are proposed. There exists a space material parameters to achieve TER ratio under constraint depolarizing field. developed an FTJ fabrication...

We have fabricated and demonstrated ultrathin In-Ga-Zn-O (IGZO) channel ferroelectric HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> field effect transistor (FET) with memory operation. Ultrathin-body IGZO FET (FeFET) shows high mobility nearly ideal subthreshold slop minimum 8 nm thickness, thanks to the properties of material, junctionless operation, nearly-zero low-k interfacial layer on metal-oxide effective capping for...

We have experimentally investigated the polarization-limited operation speed of Negative Capacitance FET (NCFET) through direct measurement negative capacitance in transient behavior ferroelectric HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> capacitor and physics-based modeling, for first time. Systematic analysis frequency dependence characteristics enabled accurate parameter extraction. With extracted parameters, our newly...

We have experimentally demonstrated a ferroelectric HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> FET with memory operation by introducing ultrathin IGZO as channel material. Ultrathin-body (FeFET) shows high mobility deposited material, nearly ideal subthreshold slope, and controllable characteristics the use of back-end compatible process. These results are attributed to properties channel: junctionless operation, nearly-zero...

A vertical channel ferroelectric-FET (FeFET) with HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> -based ferroelectric (Fe-HfO ) and atomic layer deposition (ALD) Indium oxide (InOx) has been developed demonstrated for 3D high-density memory applications. Reliable operation confirmed window (MW) >1V in gate length (L xmlns:xlink="http://www.w3.org/1999/xlink">g</sub> = 50nm short FeFETs. Polar-axis transition of Fe-HfO from in- plane...

Ferroelectric memory devices are expected for low-power and high-speed applications. HfO2-based ferroelectric is attracting attention its CMOS-compatibility high scalability. Mesoscopic-scale grains, of which size almost comparable to device size, formed in poly-crystalline thin films, largely influences electrical characteristics devices. It important study the impact mesoscopic-scale grain formation on characteristics. In this work, first, we have studied thickness dependence polarization...

The threshold voltages (Vth's) and read schemes of silicon nanocrystal memories with two bits per cell are examined by experiments simulations. It is found that the drain induced barrier lowering (DIBL) has a marked effect on Vth's in four states thus for detecting Vth's. also shown scheme can be selected controlling DIBL using device parameters including gate length, injected charge fraction, density. Suitable low-voltage low-power applications discussed.

The phase coherence length Lφ of electron waves in the one-dimensional weak localization regime was studied selectively doped AlGaAs/GaAs quantum wires fabricated by focused ion beam implantation. Estimated fitting modified theory to data is ∼1.2 μm at 0.3 K, nine times longer than n-GaAs wires. This difference well explained mobility dependence Lφ, and shows advantage structures obtain long Lφ. increased with decreasing temperature saturated below ∼3 indicating existence...

Characteristic variations of fully depleted silicon-on-insulator (SOI) MOSFETs with extremely thin buried oxide are examined by device simulations. It is found, for the first time, that a SOI low channel impurity concentration and high substrate has immunity to both parameter random dopant fluctuations (RDFs). Fully (FD) MOSFET, fluctuation (RDF), (BOX), variability.

Noise margin, characteristics of six individual cell transistors, and their variability in static random-access memory (SRAM) cells are directly measured using a special device-matrix-array test element group 16-kb SRAM cells, the correlation between noise margin transistor is analyzed. It found that each shows very different supply voltage <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex...

Single electron transport through multiple quantum levels is realized in a Si quantum-dot device at room-temperature conditions. The energy spacing of more than triple the omnipresent thermal obtained from an extremely small ellipsoidal dot, and high charge stability attained construction gate-all-around structure. These properties may move us step closer to practical applications devices elevated temperatures. An in-depth analysis on behavior structure presented.

HfO2-based ferroelectric (FE–HfO2) is a promising material for low-power and high-capacity memory technology. Since thinner films are required low voltage operation, the impact of film thickness on switching kinetics FE–HfO2 needs to be studied in detail. In this paper, metal/ferroelectric/metal capacitors fabricated with several thicknesses HfZrO2 (HZO) characterized study based nucleation limited (NLS) model. Thinner HZO show slower polarization asymmetry program erase although...

The authors describe a new narrow channel effect by quantum mechanical effects in ultra-narrow MOSFET's. Threshold voltage increase is observed at room temperature MOSFET's whose width less than 10 nm. This result excellent agreement with simulation that takes account of confinement the silicon channel, indicating threshold caused effect.

This paper proposes a new device and circuit scheme that drastically suppresses the stand-by leakage current for deep sub-0.1 /spl mu/m era while maintaining speed. Applying boosted gate voltage on low switches with higher V/sub th/ thicker T/sub ox/, extremely power battery type application is achieved, degradation of performance an increase area overhead are sufficiently suppressed. The combination negative to SRAMs also discussed.

The superior mobility in [110]-oriented ultrathin body (UTB) pMOSFETs with silicon-on-insulator (SOI) thickness (t/sub SOI/) ranging from 32 down to 2.3 nm is experimentally examined for the first time. It shown that [110] UTB pMOSFETs, which much higher than universal curve conventional (100) not degraded until t/sub SOI/ thinned 3 nm. Scattering mechanisms are discussed on basis of temperature dependence mobility. high regime pMOSFET attributed subband modulation by carrier confinement and...

The effects of quantum confinement on transport properties silicon nanowire metal-oxide-semiconductor field-effect transistors (FETs) and single-electron are experimentally investigated. By carefully designing the channel width, operate as FETs (SNWFETs) or single-charge transistors. Large in ultranarrow nanowires plays a key role these devices. We also adopt special device configuration which both n-type p-type operations can be attained an identical device, dependence direction charge...

We have shown a practical device design guideline for sub-0.2V ultra-low power, steep slope ferroelectric FET using negative capacitance (NC) focusing on operation speed, material requirement, and energy efficiency the first time. The speed is determined by finite switching time of polarization. For low supply voltage hysteresis-free design, there exists parameter window to maximize benefit NC. By optimized improved 2.5x. minimum pushed down range.

We have experimentally observed the negative-capacitance transient effect in a ferroelectric HfZrO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> (FE-HZO) capacitor and developed an equivalent circuit model based on Landau- Khalatnikov (LK) theory. By considering multiple domains (MD) domain interaction, MD-LK precisely reproduced experimental dynamic characteristics FE-HZO with various input voltage amplitude external resistance. The...

We have investigated ferroelectric phase formation of Si-doped HfO2 through nucleation and transition in the thermal process by first-principles simulation. For from amorphous thin film during annealing, tetragonal can be thermodynamically preferred with effects dopant surface energy temperature for which entropy is directly calculated phonon spectrum calculations. During cooling down, diffusionless to takes place atomic displacement monoclinic suppressed high kinetic activation barrier. The...