A5008093355- Parallel Computing and Optimization Techniques
- Low-power high-performance VLSI design
- Advanced Memory and Neural Computing
- Advanced Data Storage Technologies
- Interconnection Networks and Systems
- Radiation Effects in Electronics
- Distributed and Parallel Computing Systems
- Supercapacitor Materials and Fabrication
- Semiconductor materials and devices
- Ferroelectric and Negative Capacitance Devices
- Cloud Computing and Resource Management
Simon Fraser University
2023
Tsinghua University
2021
Georgia Institute of Technology
2020
Universidad de Zaragoza
2013-2018
Hispanics in Philanthropy
2015
Scaling supply voltage to values near the threshold allows a dramatic decrease in power consumption of processors; however, lower voltage, higher sensitivity process variation, and, hence, reliability. Large SRAM structures, like last-level cache (LLC), are extremely vulnerable variation because they aggressively sized satisfy high density requirements. In this paper, we propose Concertina, an LLC designed enable reliable operation at low voltages with conventional cells. Based on...
Power density has become the limiting factor in technology scaling as power budget restricts amount of hardware that can be active at same time. Reducing supply voltage to ultra-low ranges close threshold region promise great energy savings. However, potential savings are limited by correct operation SRAM cells, which is not guaranteed below Vddmin, minimum cache structures operate reliably. Understanding effects operating Vddmin requires complex modelling, so we introduce an updated...
Cache working-set adaptation is key as embedded systems move to multiprocessor and Simultaneous Multithreaded Architectures (SMT) because interthread pollution harms system performance battery life. Light-Power NUCA (LP-NUCA) a adaptive cache that depends on temporal-locality save energy. This work identifies the sources of energy waste in LP-NUCAs: parallel access tag data arrays tiles low locality phases with useless block migration. To counteract both issues, we prove switching serial...
As high performance computing (HPC) systems reach exascale proportions, the cost of simulation in time and resources increases. Tools for selecting representative parts parallel applications to reduce are widespread, e.g., BarrierPoint achieves this by analysing abstract characteristics such as basic blocks reuse distances. However, architectures new HPC will have a limited set tools available. In work, we provide cross-architectural evaluation, on Intel ARM, methodology used identify...
This paper makes the case for a single-ISA heterogeneous computing platform, AISC, where each compute engine (be it core or an accelerator) supports different subset of very same ISA. An ISA may not be functionally complete, but union (per engine) subsets renders platform-wide single Tailoring microarchitecture to that can easily reduce hardware complexity. At time, energy efficiency improve by exploiting algorithmic noise tolerance: mapping code sequences tolerate (any potential inaccuracy...
The importance of the interconnection network is growing as number cores integrated on a chip increases. Communication among nodes becomes bottleneck and impacts system performance power consumption. This work targets general purpose CMPs, where there rising concern about finding low-power alternatives.