Juan Salamanca

ORCID: 0000-0002-0569-2806
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About
Contact & Profiles
Research Areas
  • Parallel Computing and Optimization Techniques
  • Distributed systems and fault tolerance
  • Advanced Data Storage Technologies
  • Real-Time Systems Scheduling
  • Distributed and Parallel Computing Systems
  • Scheduling and Timetabling Solutions
  • Scheduling and Optimization Algorithms
  • Embedded Systems Design Techniques
  • Social Sciences and Policies
  • Personal Information Management and User Behavior
  • Advanced Manufacturing and Logistics Optimization
  • Innovative Human-Technology Interaction
  • Interconnection Networks and Systems
  • Vehicle Dynamics and Control Systems
  • Labor Law and Work Dynamics
  • Mobile Agent-Based Network Management
  • Vehicle Routing Optimization Methods
  • Neonatal Health and Biochemistry
  • Software System Performance and Reliability
  • AI-based Problem Solving and Planning
  • Logic, Reasoning, and Knowledge
  • Business Process Modeling and Analysis
  • Aging, Health, and Disability
  • Assembly Line Balancing Optimization
  • Semantic Web and Ontologies

Universidade Estadual de Campinas (UNICAMP)
2014-2024

Universidade Estadual Paulista (Unesp)
2019-2023

National Institute of Design
2022

Institute of Computing Technology
2016

This paper presents a detailed analysis of the application Hardware Transactional Memory (HTM) support for loop parallelization with Thread-Level Speculation (TLS) and describes careful evaluation implementation TLS on HTM extensions available in such machines. The sample over described this also provides evidence that programming effort to implement is non-trivial. Thus an extension OpenMP both makes more accessible programmers allows easytuning parameters. As result, it several important...

10.1109/tpds.2017.2752169 article EN IEEE Transactions on Parallel and Distributed Systems 2017-09-14

This paper presents a detailed analysis of the application Hardware Transactional Memory (HTM) support for loop parallelization with Thread-Level Speculation (TLS). As result it provides three contributions: (a) shows that performance issues well-known to parallelism (e.g. false sharing) are exacerbated in presence HTM, and capacity aborts can increase when one tries overcome them, (b) reveals that, although modern HTM extensions provide TLS, they not powerful enough fully implement (c)...

10.1109/ipdps.2016.84 article EN 2022 IEEE International Parallel and Distributed Processing Symposium (IPDPS) 2016-05-01

10.1016/j.jpdc.2024.104939 article EN Journal of Parallel and Distributed Computing 2024-06-15

OpenMP provides programmers with directives to parallelize DOALL loops such as parallel for and, more recently, taskloop task-based parallelism. On the other hand, when it is possible prove that a loop DOACROSS, can try through and use ordered directive mark region of has be executed sequentially. However, neither previous two cases proven, have conservative assume DOACROSS (actually may DOACROSS). Previous work proposed speculative support (tls clause) thus made exploiting parallelism fact...

10.48550/arxiv.2302.05506 preprint EN other-oa arXiv (Cornell University) 2023-01-01

Although modern compilers implement many loop parallelization techniques, their application is typically restricted to loops that have no loop-carried dependences (DOALL) or contain well-known structured dependence patterns (e.g. reduction). These restrictions preclude the of computational intensive DOACROSS loops. In such loops, either compiler finds at least one it cannot prove, compile-time, free dependences, even though they might never show-up runtime. any case, most end-up not...

10.1109/cahpc.2018.8645904 article EN 2018-09-01

Speculative Taskloop (STL) is a loop parallelization technique that takes the best of Task-based Parallelism and Thread-Level Speculation to speed up loops with may loop-carried dependencies were previously difficult for compilers parallelize. Previous studies show efficiency STL when implemented using Hardware Transactional Memory advantages it offers compared typical DOACROSS such as OpenMP ordered. This paper presents performance comparison between proposed implements (TLS) in worksharing...

10.1109/ispdc55340.2022.00021 article EN 2022-07-01

This paper describes a novel speculation technique for the optimization, and simultaneous execution, of multiple alternative traces hot code regions. technique, called Speculative Trace Optimization (STO), enumerates, optimizes, speculatively executes loops. It requires hardware support that can be provided in similar fashion as available Hardware Transactional Memory (HTM) systems. discusses necessary features to STO, namely multi-versioning, lazy conflict resolution, eager detection,...

10.1109/sbac-padw.2015.13 article EN 2015-10-01
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