With the widespread use of IoT devices in safety-critical applications, new constraints should be addressed designing infrastructures. Reliability is one most important characteristics an system which satisfied with high consideration. The way how communicate each other different layers architecture, plays role building a reliable infrastructure. Maintaining desired level reliability applications through application layer protocols, imposes noticeable amount overhead to systems. In this...

Energy consumption is a major challenge in IoT devices, which was aimed to be improved by employing energy-efficient objective functions (OFs) the structure of RPL routing protocol. Meanwhile, majority existing OFs mainly perform parent selection based on gathered information from layer. Nevertheless, our investigations, there exists series transmission operations medium access control (MAC) layer, significantly affects energy devices. Therefore, this article, we propose ELITE, an...

With the widespread use of IoT applications and increasing trend in number connected smart devices, concept routing has become very challenging. In this regard, IPv6 Routing Protocol for Low-power Lossy Networks (PRL) was standardized to be adopted networks. Nevertheless, while mobile domains have gained significant popularity recent years, since RPL fundamentally designed stationary applications, it could not well adjust with dynamic fluctuations applications. While there been a studies on...

Mobile portable embedded devices are becoming an integral part of our daily activities in the vision Internet Things (IoT). Nevertheless, due to lack mobility support IPv6 routing protocol for low-power and lossy networks (RPLs), which is standardized multihop IoT infrastructures, providing reliable communications terms packet delivery ratio (PDR) mobile applications has become significantly challenging. While several studies tried enhance adaptability RPL network dynamics, their utilized...

Spin-Transfer Torque Random Access Memories (STT-RAMs) are a promising alternative to SRAMs in on-chip caches. STT-RAMs face with high error rate write operations due stochastic switching. To alleviate this problem, Error-Correcting Codes (ECCs) commonly used, which results significant area and energy consumption overhead. This paper proposes an efficient technique, so-called Adaptive Way Allocation for Reconfigurable ECCs (AWARE), correct errors STT-RAM AWARE exploits the asymmetric cell...

Due to serious problems of SRAM-based caches in nano-scale technologies, researchers seek for new alternatives. Among the existing options, STT-RAM seems be most promising alternative. With high density and negligible leakage power, STT-RAMs open a doorto respond future demands multi-core systems, i.e., large on-chip caches. However, several should overcome make it applicable High probability write error due stochastic switching is major problem STT-RAMs. Conventional Error-Correcting Codes...

ScratchPad Memory (SPM) is an important part of most modern embedded processors. The use processors in safety-critical applications implies including fault tolerance the design SPM. This paper proposes a method, called FTSPM, which integrates multi-priority mapping algorithm with hybrid SPM structure. proposed structure divides into three parts: 1) equipped Non-Volatile (NVM) immune against soft errors, 2) Error-Correcting Code, and 3) parity. responsible to distribute program blocks among...

Spin-transfer-torque RAMs (STT-RAMs) are the most promising technology for replacing Static (SRAMs) in on-chip caches. One of major problems STT-RAMs is high error rate due to stochastic switching write operations. Cache replacement algorithms have a role number operations into Due this fact, it necessary redesign cache consider new challenges STT-RAM This paper proposes algorithm, which called least (LER), reduce L2 The main idea place incoming block line that incurs minimum operation. done...

Recent developments in non-volatile memories (NVMs) have introduced them as an alternative for SRAMs on-chip caches. Besides the promising features of NVMs, e.g., near-zero leakage power, immunity to radiation-induced particle strike, and higher density, a major drawback NVM-based caches is their short lifetime due limited write endurance. This brief first reveals that L1 caches, data-cache about 472× shorter than instruction-cache (I-cache) extreme imbalance stress between two. Then, we...

Spin-transfer torque magnetic RAMs (STT-MRAMs) are the most promising alternative for static random-access memories in large last-level on-chip caches due to their higher density and near-zero leakage power. However, reliability of STT-MRAMs is threatened by high probability read disturbance write failure. Both failure, which cause a soft error cache cells, have an asymmetric behavior. Read occurs only STT-MRAM cells storing "1" value, failure rate 0 → 1 transition much than that transition....

The standardized IPv6 Routing Protocol for Low-power and Lossy Networks (RPL) has enabled efficient communications between thousands of smart devices, sensors, actuators in a bi-directional, end-to-end manner, allowing the connection resource constraint devices multi-hop IoT infrastructures. RPL is designed to cope with major challenges (LLNs), specifically their energy-efficiency. However, facing severe congestion load balancing problems, leading low Packet Delivery Ratio (PDR) network. For...

Resource-limited mobile IoT networks are a dynamic, and uncertain wireless communicating system. In such systems, the standard RPL routing protocol cannot select long-lasting communication links due to not employing mobility-aware metrics, e.g., direction speed of movements. While several classical heuristic approaches exist improve PDR in RPL-based networks, their solutions adapt alterations topology. Hence, this paper, by mapping problem resource-limited into an infinite-time horizon MDP,...

Scratchpad memory (SPM) is extensively used as the on-chip in modern embedded processors alongside of cache or its alternative. Soft errors SPM are one major contributors to system failures, due ever-increasing susceptibility cells energetic particle strikes. Since a large fraction soft occurs shape Multiple-Bit Upsets (MBUs), traditional protection techniques, i.e., Error Correcting Code (ECCs), not affordable for protection; mainly because their limited error coverage and/or high...

Emerging STT-MRAM memories are promising alternatives for SRAM to tackle their low density and high static power consumption, but impose energy consumption reliable read/write operations. However, absolute data integrity is not required many approximate computing applications, allowing savings with minimal quality loss. This paper proposes QuARK, a hardware/software approach trading reliability of caches in the on-chip memory hierarchy multi- many-core systems running applications. In...

The increasing trend in the number of smart connected devices has turned routing procedure as one major challenges IoT infrastructures. Routing Protocol for Low Power and Lossy Networks (RPL) was introduced to satisfy different application requirements through Objective Functions (OF). Although there have been several studies on introducing new OFs order fulfill specific characteristics, e.g., energy delay efficiency, reliability, stability, but still is a lack novel which terms both,...

Recently, IoT has been massively applied in different areas of human life. Meanwhile, many the applications, e.g., remote patient health-care monitoring systems, reliability communications, and consumed energy devices, which are mostly battery-operated, very challenging. Since devices typically operated lossy environments, providing a reliable transmission for packets imposes noticeable amount consumption. In addition, runtime movement mobile networks further intensifies these issues....

STT-MRAM is regarded as an extremely promising NVM technology for replacing SRAM-based on-chip memories. While memories benefit from ultra-low leakage power and high density, they suffer some reliability challenges, namely, read disturbance, write failure, retention failure. The failure; storing a wrong value in cell during operation, the most crucial challenge. In this article, we propose ROCKY; robust architecture equipped with efficient replacement policies STT-MRAM-based cache memory...

With the widespread use of Internet Things (IoT) in every aspect human's daily life, communications such an enormous amount existing embedded devices these systems arise many new challenges from power consumption, performance, and reliability perspectives. Communications IoT infrastructure are managed by a set policies which determined Objective Functions (OFs). Thus, OFs most important contributors facing with mentioned challenges. In this paper, due to lack information on how affect...

In recent years, STT-RAMs have been proposed as a promising replacement for SRAMs in on-chip caches. Although benefit from high-density, non-volatility, and low-power characteristics, high rates of read disturbances write failures are the major reliability problems STTRAM These disturbance/failure directly affected not only by workload behaviors, but also process variations. Several studies characterized caches just one cell, vulnerability STT-RAM cannot be derived these models. This paper...

Recently, energy harvesting systems that utilize hybrid NVM-SRAM memory in their designs are introduced as a promising alternative for battery-operated systems. Since the ambient input power of an system fluctuates environmental conditions change, may stop execution programs until it receives enough to continue execution. Resuming program after suspension lead data inconsistency and threatens correct functionality programs. In this article, we propose COACH, energy-efficient...

Spin transfer torque magnetic RAM (STT-MRAM) technology is one of the most promising alternative for static (SRAM) implementing on-chip memories. Compared with SRAMs, STT-MRAMs benefit from higher density and near-zero leakage power, nonetheless they impose high energy consumption reliable write operations. However, in many applications, absolute data integrity not required; thus, acting on current applied operations may represent a novel knob disciplined approximate computing to obtain...

Tackling the dark silicon problem in a heterogeneous multicore system, temperature constraints across system should be addressed carefully by assigning proper set of tasks to pool cores during run-time. When such is utilized reliable/real-time application, reliability/timing application also augmented and make mapping more complex. To solve situation, we propose READY; an online reliability- deadline-aware scheduling algorithm for systems. READY utilizes adaptive power constraint (as metric...

With the recent development in Non-Volatile Memory (NVM) technologies, several studies have suggested using them as an alternative to SRAMs on-chip caches. However, limited endurance of NVMs is a major challenge when employed This paper proposes data manipulation technique, so-called Wearout Informed Pattern Elimination (WIPE), improve NVM-based caches by reducing activity frequent patterns. Simulation results show that WIPE improves up 93% with negligible overheads.