This article presents a coarse-grained reconfigurable cryptographic logic array named PVHArray and an intelligent mapping algorithm for algorithms. We propose three techniques to improve energy efficiency without affecting performance. First, the pipeline variable operation units balance system critical path delay number of operations ensure best Second, hierarchical interconnect network overcomes shortcomings single network, providing with good interconnectivity scalability while managing...

An Efficient and flexible implementation of block ciphers is critical to achieve information security processing. Existing methods such as GPP, FPGA cryptographic application-specific ASIC provide the broad range support. However, these could not a good tradeoff between high-speed processing flexibility. In this paper, we present reconfigurable VLIW processor architecture targeted at cipher processing, analyze basic operations storage characteristics, propose multi-cluster register-file...

A high-speed and dynamic reconfigurable hardware architecture of A5 algorithm is presented, which can satisfy the different characteristic A5/1 A5/2 algorithm. To save cost get shorter critical path, we proposed clock controlling unit output function, be reconfigured to realize function two algorithms. As method, paper performs detailed comparison analysis. The design has been realized using Altera's FPGA. Synthesis, placement routing have accomplished on 0.18 mum CMOS process, result proves...

By exploring symmetric cryptographic data level and instruction-level parallelism, the reconfigurable processor architecture for ciphers is presented based on Very-long instruction word (VLIW) structure. The application-specific instruction-set system proposed. As same arithmetic operation of ciphers, eleven kinds units are designed by technology. to requirement high energy-efficient design, loop buffer structure fetching unit proposed reduce power consumption significantly with frequency as...

In this paper a new speech privacy protection method based on sound masking and corpus is proposed. Frames in the are selected according to secret keys pitch of destination frame, frames should have same period with frame. Selected used mask original protect speech. Masked can be transmitted safely communication system. By removing effect corresponding from masked corpus, recovered. Experiment results show proposed gains good recovered quality. It robust compression by waveform coding...

In this paper, a high-flexibility and energy-efficient reconfigurable symmetric cryptographic processor architecture is presented, which based on very-long instruction word (VLIW) structure. By analyzing basic operations storage characteristics of ciphers, the application-specific instruction-set system for ciphers proposed. Eleven kinds arithmetic units are designed to support different operation modes parameters ciphers. It has been fabricated with 0.18µm CMOS technology, test results show...

This paper proposed a feedback shift register structure which can be split, it is based on research of operating characteristics about 70 kinds cryptographic algorithms and the shows that "different operations similar structure" reconfigurable design feasible. Under configuration information, implement multiplication in finite field GF(2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</sup> ), multiply/divide linear other operations. Finally,...

Aiming at the problem of energy-efficient design polynomial coefficient generation algorithms and reconfigurable units in lattice-based post-quantum cryptography, this paper investigates implements an efficient acceleration engine for multiple algorithms. In paper, we investigate discrete Gaussian sampling-based hash function-based schemes separately. For based on sampling, propose a sampling algorithm utilizing fusion tree structure, which offers greater flexibility random number...

Convolutional Neural Networks (CNN) are the most widely used in practical applications. However, with explosive growth of number CNN model parameters, large off-chip memory access becomes a bottleneck to improve energy-efficiency and performance dedicated accelerator. In this paper, per-channel processing-based accelerator domain-specific DMA structure proposed for edge computing scenario, which allows preloading parameters required next round while related operation is performing under...

Based on the characteristics of nonlinear Boolean functions operated in stream ciphers, a reconfigurable hardware architecture for these is presented, which could be reconfigured many different structures to match functions, such as Feedback shift registers and filtering functions. The this design has been realized using Altera's FPGA. Synthesis, placement routing have accomplished 0.18 ¿m COMS process. result proves that propitious carry out most ciphers published. A function 128 variables,...

A single-supply level shifter with an internal supply feedback loop, which can shift input signal from the sub-threshold to above-threshold level, is presented in this paper. This has a wider voltage conversion, less transmission delay, higher energy efficiency, and more flexibility physical layout than those described previous citations. The proposed convert 210-mV into 1.2-V output across process corners flexible when implemented 65-nm LP technology. For of 0.2 V, circuit propagation delay...

In order to enhance the performance of composite field multiplications (CFM) realized by RISC processors and VLIW processors, high-performance flexible special instructions targeted at cryptographic algorithms processing are designed in this paper. Through analyzing characteristics CFM operations different algorithms, proposed can support GF(2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">8</sup> )...

As an important branch of information security algorithms, the efficient and flexible implementation stream ciphers is vital. Existing methods, such as FPGA, GPP ASIC, provide a good support, but they could not achieve better tradeoff between high speed processing flexibility. ASIC has fast speed, its flexibility poor, flexibility, slow, FPGA resource utilization very low. This paper studies cryptographic processor which can efficiently flexibly implement variety cipher algorithms. By...

As an important branch of information security algorithms, the efficient and flexible implementation stream ciphers is vital. Existing methods, such as FPGA, GPP ASIC, provide a good support, but they could not achieve better tradeoff between high speed processing flexibility. ASIC has fast speed, its flexibility poor, flexibility, slow, FPGA resource utilization very low. This paper studies cryptographic processor which can efficiently flexibly implement variety cipher algorithms. By...

As a general interface for chip system testing and on-chip debugging, JTAG is facing serious security threats. By analyzing the typical attack model protection measures, this paper designs secure debugging based on Schnorr identity authentication protocol, takes RISCV as an example to build set of SoC prototype complete functional verification. Experiments show that has high security, flexible implementation, good portability. It can meet requirements in various application scenarios. The...

By analyzing the operation characteristic of linear feedback shifter registers (LFSRs) in many public stream cipher algorithms and its bottleneck realized by general processor, each specific instruction reconfigurable hardware cell are proposed this paper, which can neatly execute LFSR computing parallel with high performance. The instructions sustain different data widths, operating models. Instruction-level parallelism based on VLIW system structure inner several steps at one time...

In this paper, a high-efficient and low-cost secure AMBA framework utilizing the bus data encryption modeling is proposed to resist probe attacks. By encrypting confidential flowing through bus, configurable model meets security requirement of total SoC. Further, pipeline with third-level branch predictor accelerate process. Finally, an SoC 32-bit established validated 55nm technology. Experimental results show that achieves 6152Mbps throughput, consumes 39547um2 area, provides stronger...

A low power and dynamic reconfigurable hardware architecture of E0 algorithm is presented, which can satisfy sixteen different LFSRs in the Bluetooth telecommunication systems. The new LFSR design techniques be also useful any LFSR. To reduce conventional switching activity, we proposed clock-gatiing technique to implement As method, paper performs detailed comparison analysis. has been realized using Altera's FPGA. Synthesis, placement routing have accomplished on 0.18 mum CMOS process,...

To solve the problem of complex relationships among variables and difficulty extracting shared from nonlinear Boolean functions (NLBFs), an association logic model is established using classical Apriori rule mining algorithm analysis launched during variable extraction (SVE). This work transforms SVE into a traveling salesman (TSP) proposes based on particle swarm optimization (SVE-PSO) method that combines with intelligence to improve efficiency SVE. Then, according extracted various NLBFs,...

High-performance and flexible finite field X multiplications special instructions targeted at cryptographic algorithms processing are proposed in this paper, order to dispel the performance bottleneck of realized by RISC VLIW universal processors. Through analyzing characteristics different algorithms, x <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</sup> multiplication can support data widths (8 bits, 16 32 64 128 bits), k values (1~8),...