A5064472929- Advanced Memory and Neural Computing
- Parallel Computing and Optimization Techniques
- Ferroelectric and Negative Capacitance Devices
- Neural Networks and Applications
- Neuroscience and Neural Engineering
- Neural Networks and Reservoir Computing
- Neurofibromatosis and Schwannoma Cases
- Neural dynamics and brain function
- Modular Robots and Swarm Intelligence
University of California, Berkeley
2020-2024
Harvard University Press
2020
CMOS microelectrode arrays (MEAs) can record electrophysiological activities of a large number neurons in parallel but only extracellularly with low signal-to-noise ratio. Patch-clamp electrodes perform intracellular recording high ratio from few parallel. Recently, we have developed and reported neuroelectronic interface that combines the parallelism MEA sensitivity patch clamp. Here, report design characterization integrated circuit (IC), critical component interface. Fabricated 0.18-μm...
Hyperdimensional computing (HDC) is a brain-inspired paradigm that operates on pseudo-random hypervectors, an information-rich, hardware-efficient representation robust to noise and facilitates learning with limited training data. This work explores how robot navigation tasks can leverage the high-capacity hypervector enable behavioral prioritization through weighted encoding of heterogeneous sensor information. Experiments over 100 trials in each randomly generated obstacle maps demonstrate...
The remarkable advancements in artificial intelligence (AI), primarily driven by deep neural networks, are facing challenges surrounding unsustainable computational trajectories, limited robustness, and a lack of explainability. To develop next-generation cognitive AI systems, neuro-symbolic emerges as promising paradigm, fusing symbolic approaches to enhance interpretability, trustworthiness, while facilitating learning from much less data. Recent systems have demonstrated great potential...
Hyper-Dimensional Computing (HDC), a nanoscalable learning paradigm for low-energy predictions and lightweight models, has seen surge in interest from the hardware accelerator community. Its statistical distributed data representation leads to highly-efficient classifiers with inherent robustness errors. A digital, 28nm CMOS chip, representing first programmable HDC biosignal processor, achieves 25.6 nJ/pred. on leading EMG gesture recognition dataset. Measurements confirm high of HDC: 47%...