Kshitij Doshi

ORCID: 0000-0002-1927-3995
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About
Contact & Profiles
Research Areas
  • Advanced Data Storage Technologies
  • Parallel Computing and Optimization Techniques
  • Cloud Computing and Resource Management
  • Distributed systems and fault tolerance
  • Software System Performance and Reliability
  • Algorithms and Data Compression
  • Complexity and Algorithms in Graphs
  • Advanced Database Systems and Queries
  • Advanced Memory and Neural Computing
  • Interconnection Networks and Systems
  • Distributed and Parallel Computing Systems
  • IoT and Edge/Fog Computing
  • Data Management and Algorithms
  • Caching and Content Delivery
  • Machine Learning and Algorithms
  • Data Quality and Management
  • Advanced Graph Theory Research
  • Green IT and Sustainability
  • Network Packet Processing and Optimization
  • Graph Theory and Algorithms
  • DNA and Biological Computing
  • Security and Verification in Computing
  • Embedded Systems Design Techniques
  • Modular Robots and Swarm Intelligence
  • Simulation Techniques and Applications

Intel (United States)
2013-2024

Intel (United Kingdom)
2015-2018

Rice University
1985-2006

In-memory computing is gaining popularity as a means of sidestepping the performance bottlenecks block storage operations. However, volatile nature DRAM makes these systems vulnerable to system crashes, while need continuously refresh massive amounts passive memoryresident data increases power consumption. Emerging storage-class memory (SCM) technologies combine fast DRAM-like cache-line access granularity with persistence devices like disks or SSDs, resulting in potential 10x-100x gains,...

10.1109/msst.2015.7208276 article EN 2015-05-01

Non-volatile byte-addressable memory has the potential to revolutionize system architecture by providing instruction-grained direct access vast amounts of persistent data. We describe a non-intrusive controller that uses backend operations for achieving lightweight failure atomicity. By moving synchronous background, performance overheads are minimized. Our solution avoids costly software intervention decoupling isolation and concurrency-driven atomicity from durability, does not require...

10.1109/hpca.2016.7446055 article EN 2016-03-01

The identification of performance issues on specific computer architectures has a variety important benefits such as tuning software to improve performance, comparing the various platforms and assisting in design new platforms. In order enable this analysis, most modern micro-processors provide access hardware-based event counters. Unfortunately, features out-of-order execution, pre-fetching speculation complicate interpretation raw data. Thus, traditional approach assigning uniform...

10.1109/ispass.2007.363742 article EN 2007-04-01

Advances in memory technology are promising the availability of byte-addressable persistent as an integral component future computing platforms. This change has significant implications for software that traditionally made a sharp distinction between durable and volatile storage. In this paper we describe software-hardware architecture, WrAP, provides atomicity durability while simultaneously ensuring fast paths through cache, DRAM, layers not slowed down by burdensome buffering or...

10.1145/2482767.2482806 article EN 2013-05-03

In-memory database management systems (DBMSs) outperform disk-oriented for on-line transaction processing (OLTP) workloads. But this improved performance is only achievable when the smaller than amount of physical memory available in system. To overcome limitation, some in-memory DBMSs can move cold data out volatile DRAM to secondary storage. Such appears as if it resides with rest even though does not.

10.1145/2933349.2933358 article EN 2016-06-01

This paper addresses the challenges of coupling byte addressable non-volatile memory (NVM) and hardware transaction (HTM) in high-performance processing. We first show that HTM transactions can be ordered using existing processor instructions without any changes. In contrast, solutions posit changes to mechanisms form special or modified functionality. exploit ordering mechanism design a novel persistence method decouples concurrency from back-end NVM operations. Failure atomicity is...

10.1145/3092255.3092270 article EN 2017-06-09

This paper proposes a collaborative approach in which applications can provide guidance to the operating system regarding allocation and recycling of physical memory. The incorporates this decide page should be used back particular virtual page. key intuition behind is that application software, as generator memory accesses, best equipped inform about relative access rates overlapping patterns usage its own address space. It also capable steering algorithms order keep dynamic footprint under...

10.1145/2451512.2451543 article EN 2013-03-16

As it becomes ever more pervasively engaged in data driven commerce, a modern enterprise increasingly dependent upon reliable and high speed transaction services. At the same time aspires to capitalize large inflows of information draw timely business insights improve results. These two imperatives are frequently conflict because widely divergent strategies that must be pursued: need bolster on-line transactional processing generally drives towards small cluster high-end servers running...

10.1109/cyberc.2013.34 article EN 2013-10-01

Performance and energy efficiency in memory have become critically important for a wide range of computing domains. However, it is difficult to control optimize power performance because these effects depend upon activity across multiple layers the vertical execution stack. To address this challenge, we construct novel collaborative framework that employs object placement, cross-layer communication, page-level management effectively distribute application objects DRAM hardware achieve...

10.1145/2814270.2814322 article EN 2015-10-23

This paper introduces a software policy for memory management in heterogeneous systems order to improve the trade-offs between performance and power consumption, while attempting make best use of different characteristics underlying technologies. In this policy, operating system application co-schedule page informed decisions about allocation migration. Software-Controlled 2- Level Memory (Soft2LM) is hardware-agnostic approach efficient usage that allows region-based allocations,...

10.1109/nas.2016.7549421 article EN 2016-08-01

The growing popularity of hosted storage services and shared infrastructure in data centers is driving the recent interest resource management QoS systems. bursty nature workloads raises significant performance provisioning challenges, leading to increased infrastructure, management, energy costs. We present a novel dynamic workload shaping framework handle workloads, where arrival stream dynamically decomposed isolate its bursts, then rescheduled exploit available slack. show how...

10.1109/icdcs.2009.55 article EN 2009-06-01

Up-to-date business intelligence has become a critical differentiator for the modern data-driven highly engaged enterprise. It requires rapid integration of new information on continuous basis subsequent analyses. ETL-based and traditionally batch-processing oriented methods absorbing changes into relational database schema take time, are therefore incompatible with very low-latency demands realtime analytics. Instead, in-memory clustered stores that employ tunable consistency mechanisms...

10.1109/bigdata.2013.6691704 article EN 2013-10-01

Computer systems with multiple tiers of memory devices different latency, bandwidth, and capacity char­acteristics are quickly becoming mainstream. Due to cost physical limitations, device that enable better performance typically include less capacity. Such heterogeneous require alternative data management strategies utilize the capacity-constrained resources efficiently. However, current techniques often limited because they rely on inflexible hardware caching or manual modifications source...

10.1109/nas.2018.8515694 article EN 2018-10-01

Energy efficiency is an important factor in designing and configuring enterprise servers. In these servers, memory may consume 40% of the total system power. Different configurations (sizes, numbers ranks, speeds, etc.) can have significant impacts on performance energy consumption workloads. Many workloads, such as decision support systems (DSS), require large amounts memory. This paper investigates potential to save by making configuration adaptive workload behavior. We present a case...

10.1109/islped.2011.5993649 article EN 2011-08-01

Analysis of workload execution and identification software hardware performance barriers provide critical engineering benefits; these include guidance on optimization, design tradeoffs, configuration tuning, comparative assessments for platform selection. This paper uses Model trees to build statistical regression models the SPEC1 CPU2006 SPEC OMP2001 suites. These link key microarchitectural events. The detailed recipes identifying factors each suite determining contribution factor...

10.1109/ispass.2008.4510750 article EN 2008-04-01

The growing popularity of hosted storage services and shared infrastructure in data centers is driving the recent interest resource management QoS systems. bursty nature workloads raises significant performance provisioning challenges, leading to increased requirements, costs, energy consumption. We present a novel workload shaping framework handle workloads, where arrival stream dynamically decomposed isolate its bursts, then rescheduled exploit available slack. show how decomposition...

10.1109/tpds.2010.129 article EN IEEE Transactions on Parallel and Distributed Systems 2010-07-01

Energy efficiency is an important factor in designing and configuring enterprise servers. In these servers, memory may consume 40% of the total system power. Different configurations (sizes, numbers ranks, speeds, etc.) can have significant impacts on performance energy consumption workloads. Many workloads, such as decision support systems (DSS), require large amounts memory. This paper investigates potential to save by making configuration adaptive workload behavior. We present a case...

10.5555/2016802.2016864 article EN International Symposium on Low Power Electronics and Design 2011-08-01

Emerging Persistent Memory technologies (also pm, Non-Volatile DIMMs, Storage Class or scm) hold tremendous promise for accelerating popular data-management applications like in-memory databases. However, programmers now need to deal with ensuring the atomicity of transactions on resident data and maintaining consistency between order in which processors perform stores that updated values become durable.

10.1145/3240302.3240305 article EN Proceedings of the International Symposium on Memory Systems 2018-10-01

As scaling of conventional memory devices has stalled, many high-end computing systems have begun to incorporate alternative technologies meet performance goals. Since these present distinct advantages and tradeoffs compared DDR* SDRAM, such as higher bandwidth with lower capacity or vice versa, they are typically packaged alongside SDRAM in a heterogeneous architecture. To utilize the different types efficiently, new data management strategies needed match application usage best available...

10.1145/3533855 article EN ACM Transactions on Architecture and Code Optimization 2022-05-04

Controlling the distribution and usage of memory power is often difficult, because these effects typically depend on activity across multiple layers vertical execution stack. To address this challenge, we construct a novel collaborative framework that employs object placement, cross-layer communication, page-level management to effectively distribute application objects in DRAM hardware achieve desired power/performance goals. This work describes design implementation our framework, which...

10.1145/3196886 article EN ACM Transactions on Architecture and Code Optimization 2018-05-01

As data centers and end users become increasingly reliant on virtualization technology, more efficient accurate methods of profiling such systems are needed. However, under the virtual machine OS each try to manage same resources independently, underlying hardware is now multiplexed between many streams execution, non-trivial interference can be caused by seemingly unrelated resources. While sampling techniques effective at gathering average behaviors over long runs, understanding...

10.1109/hicss.2010.440 article EN 2010-01-01

By providing instruction-grained access to vast amounts of persistent data with ordinary loads and stores, byte-addressable storage class memory (SCM) has the potential revolutionize system architecture. We describe a non-intrusive SCM controller for achieving light-weight failure atomicity through back-end operations. Our solution avoids costly software intervention by decoupling isolation concurrency-driven from durability, does not require changes front-end cache hierarchy. Two...

10.1109/lca.2015.2443105 article EN IEEE Computer Architecture Letters 2015-06-10
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