The main objective of this paper aims at designing an efficient blind assistance system for the visually impaired people using real time disparity estimation algorithm. local window based matching algorithms known as sum absolute differences (SAD) and zero-mean SAD (ZSAD) are used hardware architectures those implemented in FPGA. ZSAD image resolution 640x360 pixels with square size 8x8 a range 0 to 99. An line buffering scheme left right two camera images is support parallel processing...

Analog Comparator is designed to compare two analog inputs and outputs a logical signal indicating which of the greater or lesser. Comparators, being an essential building block most high speed devices like Analogue Digital Converters, are one important components used in processing communication systems. Also it plays challenging role mixed system designs. In this paper, we have presented ultra-high simple dynamic comparator design using 65nm UMC technology. The circuit operating at clock...

The requirements of hardware design for large integer polynomial multiplications is the need hour in various cryptographic fields involving computational complexities. Schoolbook multiplication, being a common alternative presented this paper implementation. A highly optimized multiplier proposed, which much faster than traditional ones. overall performance algorithm evaluated using Area-Time-Product (ATP). Hardware implementation proposed schoolbook multiplication architecture done Virtex-7...

The paper is concerned with calculation of the small-signal admittance parameters field-effect transistors in general. For this purpose, it first shown that can be effectively treated as a special class analogue RC transmission lines, which resistance uniformly distributed but capacitance nonuniformly distributed. difficulty analysing type line resolved by assuming piecewise uniformity good first-order approximation. matrix method analysis employed. This has been found to simple and rapid...

The conventional MOS current mode logic (MCML)-based multiplexer needed for serializer application has various limitations, such as low voltage-swing, substantial power consumption, and large area overhead. In the circuit arrangement of a using MCML-based mux-tree concept, output one mux at any stage is used to feed another next through some latch circuits, which are basically timing synchronization giving away penalty in terms delay area. increase number stages Serializer may lead further...

Fluoride is one of the parameters which non-degradable and naturally occurring inorganic anion found in many natural streams, lakes, groundwater. Serious problems are faced several parts India due to high consumption fluoride through drinking water. These may cause dental skeletal fluorosis humans. This study aims examine level both Bharalu river water groundwater within Guwahati city, Assam, India, also analyze impact reach on aquifer adjacent river. From investigation, it has been observed...

Useful expressions for the small-signal forward- and reverse-transfer parameters of metal-oxide-semiconductor junction-gate field-effect transistors are derived from a simple unified charge-control analysis which is also applicable to bipolar transistor. Basic compared. It shown that, although physical mechanisms involved in operation these three types transistor distinctly different, their electrical equivalent-circuit representation significance associated identical.

In this paper a design methodology for novel robust adaptive integral backstepping controller the motion control system, has been presented in systematic manner. Backstepping is realistic nonlinear algorithm based on Lyapunov approach, as consequence it automatically ensures convergence of regulated variable to zero. Adaptation schemes are designed estimate inertia variation and load disturbance systems. Integral action being used enhance steady state against disturbances. We explore concept...

As the high speed electronic systems are in midway of getting shifted from conventional parallel data transmission to new rate serial link, design an unit cell (i.e. MUX) for serializer interface has become area interest. In this paper, we have demonstrated current mode logic based novel 2:1 multiplexer featuring dual latch be steered by either CLK or CLKBAR. The approach is simulated 90nm CMOS technology using Cadence Virtuoso platform at a power supply 1Volt with 10GHz switching frequency....

The demand for efficient large integer polynomial multiplications in present day crypto-systems is the need of hour. Karatsuba-like multiplication one most algorithm discussed this work. However, mostly practically avoided due to presence complex sub-multiplications at intermediate steps computation. Thus, efforts has been made implement two-term Karatsuba Multiplication (Method-I & Method-II), i.e., TTKM-I and TTKM-II terms speed hardware utilization. overall performance proposed design...

The current demand for efficient multiplication of large integer polynomials in contemporary cryptographic systems is crucial. This work explores the Karatsuba-like multiplication, recognized as one most algorithms. Despite its efficiency, this algorithm often avoided practice due to complexity sub-multiplications during intermediate computation steps. Consequently, efforts have been directed towards implementing asymmetrical and symmetrical five-term Karatsuba Multiplication, denoted as:...

It is essential to have efficient large integer multiplications for current cryptosystems. Karatsuba-like multiplication one of the most algorithms, but mostly avoided due complex sub-multiplications. Thus, efforts has been made implement eight-term Karatsuba Multiplication (Method-II), i.e., ETKM-II in terms speed and hardware utilization. The overall performance proposed design methods are noted by calculating Area-Time-Product (ATP) compared with conventional (CETKM) existing...

The nonlinear differential equations describing the large-signal switching behaviour of field-effect transistors (f.e.t.s) are derived. They shown to be analogous those an RC transmission line having uniform linear resistance but capacitance per unit length. Solutions these equations, based on effective linear-capacitance approximation, obtained and applied cases metal-oxide-semiconductor (m.o.s.t.s) junction-gate transistors. It is experimentally established that there little difference...

Modern cryptographic algorithms demand the use and necessity for large integer polynomial multiplications. However input operand size of multipliers, complexity hardware design arises in terms space time. Thus, this paper efforts has been made to an efficient multiplier by implementing a hybrid Karatsuba multiplication algorithm. The overall performance proposed is measured using Area-Time-Product (ATP). Hardware implementation architecture done Virtex-7 FPGA device Xilinx ISE platform.