Potholes are one of the roadway distresses that negatively impact safety. With emerging sensing technology, three-dimensional (3D) pavement data, derived using 3D laser have become available for detecting cracking and rutting. This paper presents a pothole detection method data watershed method. Tests collected on 10th Street, Atlanta, Georgia 6 mi U.S. 80, Savannah, Georgia, has shown 94.97% accuracy, 90.80% precision, 98.75% recall. It been demonstrated proposed is promising can provide...

At low frequencies, alternate testing is based on sampling the test response using an A/D converter and analyzing digitized in external tester. In order to use at frequencies multi-GHz range, where above not possible, waveforms need be very simple evaluation of needs handled by on-chip analog "feature extractors". this work, specialized functions output from are computed built-in feature extraction sensors, which measure a complex function waveform DC signature. Different sensor structures...

Because of aggressive technology scaling and multi-GHz operating frequencies radio frequency (RF) devices, parametric failure test diagnosis RF circuitry is becoming increasingly important for the reduction production cost faster yield ramp-up. A low-cost method proposed multi-parametric faults in wireless systems that allows accurate prediction end-to-end specifications as well all embedded modules. The procedure based on application an optimised stimulus extraction its transient response...

Three-dimensional (3D) laser scanners have become a mainstream technology for the automatic assessment of pavement condition. The objective this study is to leverage highly accurate 3D data train supervised machine learning models condition estimation using low-cost vehicle-mounted smartphone sensor data. First, and were registered on common geographic information system (GIS) model road network. Second, recurrent neural networks (RNNs) with long short-term memory (LSTM) units trained...

This paper proposes a novel methodology for reducing the static linearity test time of SAR A/D converters. Due to low data conversion rate and high resolution, required measuring specifications such as INL DNL in converters can be 40% total converter time. The proposed method is based on fact that non-idealities code widths are correlated dominated by manufacturing variations specific components used design. Therefore, subset set directly affected these components, all estimated accurately....

Automated pavement crack detection is essential to a cost-effective asset management system. Many automated algorithms (CDAs) have been developed, but they lack standardized performance evaluation system, which urgently needed. This paper presents comprehensive, quantitative CDA system (CDA-PES) that includes: (1) an enhanced Hausdorff distance–based method; (2) consistent data set designed with diverse types and conditions affect performance; (3) multilevel, categorized, scoring reporting...

Over the last 20 years, several crack detection algorithms have been developed to implement safe and efficient automated road condition survey (ARCS) systems. Although current state-of-the-art can achieve a high level of accuracy, their computation time makes them infeasible in real-time without massive parallelization. This paper presents fast accurate algorithm. The algorithm consists following major steps: 1) Image preprocessing; 2) Preliminary segmentation minimize false negatives; 3)...

In this paper, we propose a framework for analyzing the effects of circuit parameter variations on high level system specifications in hierarchical manner. The one design hierarchy those next are mapped through linear and piecewise sensitivity functions. models allow computation statistical distributions parameters their correlations. This data is used to determine critical that must be measured may eliminated from testing process.

In this paper, a novel algorithm has been proposed to measure system specifications of an integrated transmitter, which capture the non-linearities system-under-test. The measurement these is important, as determine amount "interference" created by transmitting in adjacent channels while data specific channel. By using optimized periodic bit stream, with energy concentrated at fewer frequencies, all interest are measured. This requires measurements and hence, significantly reduced test time...

A hierarchical diagnosis algorithm is presented for testing identical units in a system. As all are similar, it essential that the test process be parallelized to enable of multiple cost one unit. With this objective mind, we propose novel architecture consisting hierarchy testers system simultaneously. In approach, special chips placed at strategic locations compute "golden response" by analyzing responses units. The propagated up testers. At each level, analyze data and pass golden...

Reference spur is a nonlinear effect and important specification in PLL for long term jitter. Periodic events of reference clock create static phase offset between signals. The finite comes from charge pump mismatch layout asymmetry. This paper presents built-in self-test (BIST) circuit applied (SPO) estimation. proposed takes advantage an integrator time-to-voltage conversion (TVC). Along with comparators counters, BIST can be constructed estimation ratio down to 1% over process corners...

Signal processing based automated road condition surveys (ARCS) system are the solution for current unsafe, subjective and labor-intensive manual surveys. Although extensive research has been conducted on methods ARCS, application by transportation agencies is still minimal. In 2016, an ARCS system, developed Georgia Tech, was successfully implemented a 4,184km highway in Georgia, USA. This paper presents insights gained from project also discusses remaining challenges with focus crack...

In this paper we propose a simulation-based analog circuit sizing method which is capable of significantly reducing the computational cost via adaptive response surface modeling. The proposed algorithm based on selective evaluation model coupled with numerical simulation and update for accuracy. An effective sampling scheme modeling using two related criteria that are crucial speedup convergence towards an optimal solution presented. One provides sufficient samples accuracy convergence,...

With the increasing availability of huge quantities manufacturing data, and pressures continuous process improvement scrap reduction, engineers are beginning to use machine learning techniques along with traditional statistical methods. In this paper, we discuss application standard analyze, classify, predict quality metal etch using RIE. Three types data were used characterize a etch: in-process sensor from chamber, metrology for critical dimension measurements before after etch, resistance...

In this paper, we propose a novel simulation-based analog circuit sizing method, which is capable of significantly reducing the computational cost via adaptive response surface modeling. The proposed algorithm based on selective evaluation model coupled with numerical simulation and update for accuracy. Efficient sampling scheme modeling, that crucial speedup convergence into optimum solution, done two criteria cascaded. One provides sufficient samples accuracy convergence, whereas other...

Fast analog fault simulation is critical in test development and diagnosis for mixed-signal circuits. It has been demonstrated that concurrent methods can greatly reduce the computational complexity of by sharing intermediate results between different faults. In this paper we present an algorithm dynamic grouping transient nonlinear The goal general to minimize total running time all faulty circuits while satisfying accuracy constraints. Fault allows subset faults with similar response...

Test generation for scan-based test of sequential circuits is typically performed by generating tests the embedded combinational logic (ECL) and translating these into scan vectors. However, serial nature incurs significant overhead in terms application time. To reduce data volume, this paper we propose a new algorithm compatibility analysis circuit flip flops. This algorithm, when applied to parallel-scan methods such as Illinois Scan Architecture (ILS), results shorter more balanced...

A boundary scan-based algorithm is presented for testing iterative arrays of identical units such as integrated circuits on silicon wafers, MCMs fabricated a large area panel, and multiprocessor systems. As all the are similar, it critical that test process be parallelized in order multiple may tested cost one unit. With this objective mind, we propose parallel pipelined scan standard-based scheme simultaneously. In scheme, vectors corresponding correct-response both scanned into chain an...

A new low-cost technique for jitter measurement of phase-locked loops (PLLs) is described. The proposed can be applied to PLLs whose predominantly due power supply noise. Accurate picosecond accuracy using conventional methods requires very high-cost tester instrumentation. By modulating the voltage PLL and noting that extremely sensitive variations, it possible introduce significant into output which measured a During production test, regression model used predict inherent from induced jitter.

The recent increase in demand within the wireless user community for short-range, very high rate data transmission (data, video) devices has spurred growth of a new generation 4G devices, viz. ultra-wideband (UWB). Due to its wide band operation (3.1-10.6GHz) and non-conventional transmit/receive scheme (using short-duration, narrow baseband pulses), spectral power leakage outside frequency bands causes interference with other standards. In this paper, we focus on 'out-of-band' testing UWB...

In this paper, a low-cost test methodology for dynamic specifications of high precision sigma-delta (ΔΣ) analog-to-digital converters (ADCs) is presented. Dynamic testing ADCs requires an input stimulus with total harmonic distortion (THD) and signal-to-noise ratio (SNR) about 10dB better than the ADC under test. ΔΣ are inherently resolution excellent THD SNR due to their inherent over-sampling, averaging noise shaping properties. proposed methodology, back end digital decimation filters...

This paper addresses the issue of testing MCMs fabricated on large-area substrates. The cost may be as high 40% manufacturing cost. In order to reduce test costs, at is essential that parallelized taking advantage fact all substrate are similar. this we propose a hierarchical probabilistic algorithm for method, divided into clusters. responses analyzed within their clusters, and most common sent global tester determining likely correct response. Based this, diagnosed faulty or fault free....