The increasing demand for higher network data rates by new businesses and entertainment has never been fulfilled. Mixed-signal PAM - 4 transceivers prevail over their ADC DSP counterparts in energy efficiency chip area, but they have difficulties operating high loss links. Typically, a continuous-time linear equalizer (CTLE) multi-tap decision-feedback (DFE) are implemented mixed-signal receiver (RX). However, when the rate reaches 112Gb/s, implementation of DFE suffers from stringent...

A novel parameter identification method with dynamic impedance regulation is proposed to maintain constant output voltage of wireless power transfer (DWPT) system under varied loads and mutual inductance conditions. The resonant capacitor in the receiver side replaced a switched-controlled (SCC) structure, which enables work two operation modes. And then comprehensive mathematical model established according these modes achieve identification. To avoid deterioration accuracy caused by...

This article presents a four-level pulse-amplitude modulation (PAM-4) transceiver targeting very-short-reach and medium-reach (MR) electrical links. The receiver (RX) employs sample-based four-tap feed-forward equalizer (FFE) for pre- post-cursor inter-symbol interference (ISI) compensation. two-stage 16-way interleaving provides sufficient operation time FFE summation, which relaxes the bandwidth (BW) requirement improves power efficiency. non-uniform segmented three-tap reduces parasitic...

This paper proposed two modified analysis methodologies based on the fundamental harmonics approximation (FHA) and Simplified Time Domain Analysis (STDA). The equivalent output resistance of resonant tank in discontinuous conduction mode (DCM) is derived, this FHA (MFHA) shows more accuracy than DCM, especially when working frequency far away from series frequency. In meantime, STDA (MSTDA) MFHA STDA, which also accurate as close to Finally, a prototype was built according parameter design...

The ever-growing demands for high-bandwidth communications continuously push wireline links to operate at higher speeds. Recently reported transmitters (TXs) have achieved a data rate of more than 100Gb/s [1–6]. PAM-4 modulation, which doubles the same symbol rate, has been widely adopted make use link bandwidth efficiently. However, complex transitions introduce greater data-dependent jitter, decreasing horizontal eye-opening. In addition, between non-adjacent levels bring about twice or...

Coherent detection with polarization multiplexing is widely used because of its high spectral efficiency. However, it utilizes analog-to-digital converters (ADCs) and digital signal processing (DSP), which consume a large amount power thereby hinder application in power-sensitive short-reach links. In this article, we present 200-Gb/s analog <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$C$...

Zero-phase-angle (ZPA) operation is considered as a method to minimize the volt-ampere (VA) ratings and maximize transfer power load in inductive (IPT) system. However, ZPA operating prerequisite quite sensitive variation of parameters such IPT system coupling coefficient conditions. A parallel-series/series (PS/S) current-fed with new variable capacitors (VCs) structure proposed achieve constant output voltage at fixed frequency. The detailed analysis mathematical model VCs network are...

Emerging bandwidth-hungry applications such as cloud computing, have significantly driven the requirement for high transmission data rates. Polarization diversity coherent detection is an indispensable technique realizing high-capacity owing to its excellent spectral efficiency. ADC-DSP-based receivers [1]–[2] been widely deployed in long-haul optical systems, but power consumption prohibits their application power-sensitive short-reach links like 5G mobile backhaul networks, arousing...

A 14GHz CML-based phase interpolator (PI) is proposed for a 4-way time-interleaved 56Gbaud clock and data recovery (CDR). The has resolution of 7 bits implemented in 28 nm CMOS technology with 1.0V power supply. PI consists controller, slew-rate-control buffer, mixer. distribution the tail current sources, short-channel effect, slew rate input signals are analyzed several methods to optimize interpolation linearity. measured integral non-linearity (INL) calculated differential (DNL) less...

A 14GHz digitally controlled oscillator (DCO) is proposed for all-digital phase-locked loop (ADPLL). With a cascade differential-capacitor array, the resolution of DCO enhanced, which leads to decrease in quantization noise, while area cost and substrate noise are also significantly reduced. In addition, resistor-biased output buffer used cut down phase by eliminating flicker thermal conventional current-mirror structure brings. The designed 14nm FinFET process, achieving -110dBc/Hz at 1MHz...

To investigate the advantages of adjustable angle needle path template compared with CT-guided

To meet the urgent requirements of safety surveillance from civil engineering management authorities, this study proposes a refined and efficient approach to generate full-field high-resolution panorama construction sites using cameraamounted UAV (Unmanned Aerial Vehicle). GPS (Global Position System) information extraction for pre-registration, feature points filtering registration optimal seaming line seeking fusion are performed in sequence form generation framework. Advantages proposed...

A novel structure of analog signal processing circuits for coherent receivers is proposed and implemented in 28-nm CMOS technology with 1V supply voltage this work. To avoid excessive taps equalizer or prolix circuit modules, the system combines crosstalk carrier phase recovery application 2 kinds multipliers to compensate linearity higher accuracy. In order achieve stronger converging ability, simplify realization further reduce power dissipation, chromatic dispersion uses DFE instead FFE...

As the data transmission demand increases, time margin for receiver sampling becomes smaller rapidly. Particularly at 224Gbps node, overall may be less than 1ps. Since IUI-spaced feed-forward equalizer and decision-feedback cannot equalize frequency responses above Nyquist in theory, continuous-time linear only module wireline receivers that increases eye width. This paper constructs a bit-by-bit time-domain model of discusses relation between poles diagram. The simulation results show when...

In order to achieve good transmission characteristics of ICPT system, zero-phase-angle (ZPA) operation and constant voltage output are always required. However, the operating point is significantly affected by variation magnetic coupling load conditions. This paper presents a two-degree-of-freedom control strategy for parallel-series/series IPT network. ZPA achieved controlling phase shift angle switched capacitor. On this basis, new three-level current proposed output. The detailed...

This paper presents a 40Gb/s PAM4 baud-rate clock and data recovery (CDR) with equal-slope (ES) algorithm. Comparing to MM-CDR, whether equipped feedforward equalizer (FFE) on transmitter (TX) side or not, ES-CDR has advantages in recovered eye-height timing margin by optimizing sampling point, while avoiding extra hardware cost. Realized 28nm CMOS process, the showcases x7 orders of magnitude lower bit error rate (BER) for 12dB loss at PAM4.