A5026531367- Low-power high-performance VLSI design
- VLSI and FPGA Design Techniques
- Electromagnetic Compatibility and Noise Suppression
- VLSI and Analog Circuit Testing
- Analog and Mixed-Signal Circuit Design
- Advancements in Semiconductor Devices and Circuit Design
- Antenna Design and Analysis
- Microwave Engineering and Waveguides
- Advancements in PLL and VCO Technologies
- Parallel Computing and Optimization Techniques
- Radiation Effects in Electronics
- CCD and CMOS Imaging Sensors
- Semiconductor materials and devices
- 3D IC and TSV technologies
- Radio Frequency Integrated Circuit Design
- Advanced Data Compression Techniques
- Microwave Imaging and Scattering Analysis
- SARS-CoV-2 detection and testing
- Antenna Design and Optimization
- Meningioma and schwannoma management
- Interconnection Networks and Systems
- Embedded Systems Design Techniques
- Video Coding and Compression Technologies
- Wireless Body Area Networks
- Quantum Computing Algorithms and Architecture
Guru Nanak Institutions
2021-2024
Vels University
2021
Chaitanya Bharathi Institute of Technology
2019-2020
Yes Technologies (United States)
2020
National Institute of Technology Durgapur
2010-2019
Armed Forces Medical College
2019
Southern Command Hospital
2019
Apeejay Stya University
2012-2013
Hindustan Institute of Technology and Science
2011-2012
Anand Agricultural University
2012
Increasing the growth of big data, particularly in healthcare-Internet Things (IoT) and biomedical classes, tends to help patients by identifying disease early through methods for analysis medical data. Hence, nanotechnology-based IOT biosensors play a significant role field. Problem. However, consistency continues decrease where missing data occurs such from biosensors. Furthermore, each region has its own special features, which further lowers accuracy prediction. The proposed model...
GDI (Gate Diffusion Input) is a new technique of low power digital circuit design proposed. This allows minimization area and consumption circuits. In this XOR gate designed using 3 transistors CMOS full adder based on two 3T one 2T Mux. Using 8 the in paper voltage scaling also done by reducing supply voltage. proposed adder, 4.604μW achieved total 144μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .
<p>The objective of this research paper is to propose the design an integrated circuit (IC) combined with antenna reduce footprint on Printed Circuit Board (PCB). The aim enhance its power, space efficiency, and sustainability in order improve usefulness, especially smart city communication. This introduces a that enables message transmission reception through multiple channels while also facilitating wireless spectrum sharing over 5G network. effectiveness sustainably designed 2 ×...
This paper describes a high-performance WLAN 802.11a/b/g radio transceiver, optimized for low-power in mobile applications, and co-existence with cellular Bluetooth systems the same terminal. The direct-conversion transceiver architecture is each mode operation without compromising challenging RF performance targets. A key requirement sensitivity of -77 dBm (at LNA input) 54 Mb/s OFDM while presence GSM1900 transmitter interferer. receiver chain achieves an overall noise figure 2.8/3.2 dB,...
A 450-MOPS video decoder that decompresses both H.261 and MPEG (Motion Picture Experts Group) compressed streams is described. The accepts bit rates up to 4 Mb/s provides decoded frames of 352*288 pixels (CIF) at 30 frame/s operating 45 MHz. places no restrictions on the streams. It decodes any combination intra predictive in QCIF or CIF format. In mode, it stream conforming constrained parameters, including intra, predictive, bidirectional with half-pixel motion vectors. architecture...
GDI technique allows minimization of area and power consumption digital circuits. The reversible gate preserves same parity between output input vectors is called fault tolerant but the dimension should be 3. In this design, Peres Gate designed using Diffusion Input 8 transistors. proposed new used to design full adder with efficient tolerant. work 51.62μW achieved for supply voltage 1V total 492μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML"...
This paper describes a low-power, high-performance WLAN 802.11 a/b/g radio transceiver optimized for mobile applications and co-existence with on-board cellular Bluetooth systems. The direct conversion architecture is to achieve uncompromised RF performance at low power. A key requirement sensitivity of -77dBm (at the LNA input) in presence GSM 1900 transmitter interferer while 54Mb/s OFDM mode. receiver chain achieves NF 2.8/3.2dB, consuming 168/185mW 2.8V 2.4/5GHz bands respectively....
In modern fabrication techniques, it is possible to fabricate nanostructure based semiconductor devices whose dimensions are much more comparable the de Broglie wavelength of electron. Therefore concept tunneling a key point parameter in design and nanoelectronic devices. Particle tunnels through barrier particularly presence high electric field or when thin. Leakage nano MOSFET due phenomena energy electron super narrow oxide barriers. The theory from metal was given by Fowler Nordheim....
A novel heterostructure metal-insulator-semiconductor (MIS) diode is proposed and studied theoretically to examine the effect of illumination on characteristics device. The capacitance structure has been calculated in dark as well various illuminated conditions. It found that MIS can be controlled by varying incident light intensity. By incorporating capacitor tuned circuit an oscillator it will possible convert intensity-modulated optical signal. device also expected find useful application...
With continuous scaling of VLSI technology, coupling capacitance between interconnects lines need more accurate transmission line modelling, requiring the introduction self and mutual inductances. Self inductances can cause for crosstalk noise delay high speeds interconnects. This paper presents an mathematical computation `L' Type RLC global in presence analysis is carried out case when two L type networks are parallel to each other but not connected, Step input applied aggressor which...
A 54-year-old female patient had a sudden onset of febrile illness following which she developed low backache and paraplegia with urinary retention. Her hemogram, biochemistry, coagulation profile was within normal limits. dengue serology positive for IgG antibodies but negative NS1 Ag. Magnetic resonance imaging dorsolumbar spine revealed extensive subdural bleed from D6-D12 cord compression. She underwent emergency laminectomy along complete evacuation hematoma. There recovery sensations...
As the technology scales down to nanometer regime, interconnect delay is more dominant than gate delay. Many approaches primarily concentrated find rather so that one can increase speed of circuit by simply decreasing Several have been proposed accurately and efficiently. By considering impulse responses linear as a Probability Distribution Function (PDF), Elmore first estimated value after Delay metric like PRIMO, AWE, h-gamma, WED, D2M etc. are proven be accurate metric. But they suffer...
In case of very high frequency as in Giga-scale (GHz), no longer can interconnects be treated mere delays or lumped RC networks. The most common simulation model for is the distributed and RLC model. impact on circuit performance both analog digital domains ever increasing. Unfortunately, this has many limitations which lead to inaccurate simulations if not modeled correctly. Crosstalk, ringing reflection are just some issues that need addressed then circumvented utilized. traditional...
Moments of the impulse response are widely used for interconnect delay analysis, from explicit Elmore (the first moment response) expression, to matching methods which creates reduced order trans-impedance and transfer function approximations.However, is fast becoming ineffective deep submicron technologies, delays impractical use as early-phase design metrics or optimization cost functions.This paper describes an approach fitting moments probability density functions so that can be...
The main objective is to detect and reduce the faults in full adder design using self checking repairing block. rate of chip failure directly proportional density. This fault tolerant has high speed (Delay 6.236ns) & implemented on FPGA Spartan 3 XC3S50 device. source code written verilog. In this are identified repaired methodologies.
The main objective is to detect and reduce the faults in full adder design using self checking repairing block. rate of chip failure directly proportional density. This fault tolerant has high speed (Delay 6.236ns) & implemented on FPGA Spartan 3 XC3S50 device. source code written verilog. In this are identified repaired methodologies
This paper presents a new method to estimate the crosstalk noise for on-chip VLSI RLC global interconnects using 2-π model. Distributed can be modelled an above low frequency operation with sufficient accuracy and better result. To calculate this we apply unit step input aggressor network side which is adjacent victim network. proposed model voltage waveform by generated at output of also gives idea peak amplitude width interconnects. Some mathematical technique are calculating interconnect....
This paper presents an accurate, fast and simple closed form solution to estimate crosstalk noise between two adjacent wires in VLSI circuits, using RLC interconnect model. Noise analysis avoidance techniques are critical steps deep submicron technology. Currently performed either through circuit or timing simulation. These still inefficient for analyzing massive amount of data found present day integrated circuit. efficient technique estimation coupled on-chip interconnects. metric is upper...
This paper proposes a much improved, accurate, fast and simple crosstalk model for coupled interconnect line considering the skin effect. It is time VLSI designers to examine noise effects in their designs, so that they are free from noise. Hence, accurate modelling RLC lines critical timing system integrity analysis. Skin effect alters values of resistance also inductance, which turn affects particular its response as whole. Till now has been neglected on-chip interconnects. addresses novel...
Due to high packaging density of components, delay modelling is increasingly becoming the bottleneck for design performance VLSI circuits. At higher frequency operations, order few GHz, on-chip interconnect be analyzed with a distributed RLCG model. Because at very frequency, dielectric material deviates from its ideal nature. This gives rise shunt conductance matrices. The Elmore can deviate typical interconnections ramp input SPICE computed delay. Since it independent time signal. In...
In this paper, we begin with the analysis of signal delay through an ideal RLCG transmission line model, without driver and load impedance. This yield's to transform voltage current equations governing system response by incorporating appropriate boundary conditions for interconnect analysis. Two port parameters in terms ABCD matrix are obtained. Further, considered a practical find relation between input output s-domain. The thus obtained is applied step transient it time domain using...