A5047443783- Parallel Computing and Optimization Techniques
- Advanced Data Storage Technologies
- Interconnection Networks and Systems
- Radiation Effects in Electronics
- Embedded Systems Design Techniques
- Distributed and Parallel Computing Systems
- Security and Verification in Computing
- Low-power high-performance VLSI design
- Cloud Computing and Resource Management
- Logic, programming, and type systems
- Distributed systems and fault tolerance
- Model-Driven Software Engineering Techniques
- Formal Methods in Verification
- Advanced Malware Detection Techniques
- Semiconductor materials and devices
- Software Engineering Research
- Optical Network Technologies
- Advanced Software Engineering Methodologies
- Risk and Safety Analysis
- Scientific Computing and Data Management
- Photonic and Optical Devices
- Superconducting Materials and Applications
- Business Process Modeling and Analysis
- Advanced Memory and Neural Computing
- Radioactive element chemistry and processing
University of Cambridge
2016-2025
Universidad de Murcia
2025
Barking, Havering And Redbridge University Hospitals NHS Trust
2024
Victoria University of Wellington
2013-2017
Harvard University Press
2014
Louisiana State University
2013-2014
Louisiana State University Agricultural Center
2014
University of Edinburgh
2005-2012
University of Siena
2011
Data61
2010
The microarchitectural design space of a new processor is too large for an architect to evaluate in its entirety. Even with the use statistical simulation, evaluation single configuration can take excessive time due need run set benchmarks realistic workloads. This paper proposes novel machine learning model that quickly and accurately predict performance energy consumption any programs on configuration. architecture-centric approach uses prior knowledge from off-line training applies it...
Building an optimising compiler is a difficult and time consuming task which must be repeated for each generation of microprocessor. As the underlying microarchitecture changes from one to next, retuned optimise specifically that new system. It may take several releases effectively exploit processor's performance potential, by has appeared process starts again.
We describe and evaluate HELIX, a new technique for automatic loop parallelization that assigns successive iterations of to separate threads. show the inter-thread communication costs forced by loop-carried data dependences can be mitigated code optimization, using an effective heuristic selecting loops parallelize, helper threads prefetch synchronization signals. have implemented HELIX as part optimizing compiler framework automatically selects parallelizes from general sequential programs....
The disclosure of the Spectre speculative-execution attacks in January 2018 has left a severe vulnerability that systems are still struggling with how to patch. solutions currently exist tend have incomplete coverage, perform badly, or highly undesirable edge cases cause application domains break. MuonTrap allows processors continue speculate, avoiding significant reductions performance, without impacting security. We instead prevent propagation any state based on speculative execution, by...
Searches on large graphs are heavily memory latency bound, as a result of many high DRAM accesses. Due to the highly irregular nature access patterns involved, caches and prefetchers, both hardware software, perform poorly graph workloads. This leads CPU stalling for majority time. However, in cases data pattern is well defined predictable advance, falling into small set simple patterns. Although existing implicit prefetchers cannot bring significant benefit, prefetcher armed with knowledge...
Adaptive micro architectures are a promising solution for designing high-performance, power-efficient microprocessors. They offer the ability to tailor computational resources specific requirements of different programs or program phases. have potential adapt hardware cost-effectively at runtime any application's needs. However, one key challenges is how dynamically determine best architecture configuration given time, new workload. This paper proposes novel control mechanism based on...
A lack of temporal safety in low-level languages has led to an epidemic use-after-free exploits. These have surpassed number and severity even the infamous buffer-overflow exploits violating spatial safety. Capability addressing can directly enforce for C language by enforcing bounds on pointers rendering unforgeable. Nevertheless, efficient solution strong memory remains elusive.
Intelligently partitioning the last-level cache within a chip multiprocessor can bring significant performance improvements. Resources are given to applications that benefit most from them, restricting each core number of logical ways. However, although overall is increased, existing schemes fail consider energy saving when making their decisions. This paper presents Cooperative Partitioning, runtime scheme reduces both dynamic and static while maintaining high performance. It works by...
Use-after-free violations of temporal memory safety continue to plague software systems, underpinning many high-impact exploits. The CHERI capability system shows great promise in achieving C and C++ language spatial safety, preventing out-of-bounds accesses. Enforcing language-level on requires revocation, traditionally achieved either via table lookups (avoided for performance the design) or by identifying capabilities revoke them (similar a garbage-collector sweep). CHERIvoke, prior...
Data dependences in sequential programs limit parallelization because extracted threads cannot run independently. Although thread-level speculation can avoid the need for precise dependence analysis, communication overheads required to synchronize actual counteract benefits of parallelization. To address these challenges, we propose a lightweight architectural enhancement co-designed with parallelizing compiler, which together decouple from thread execution. Simulations approaches, applied...
Many modern workloads compute on large amounts of data, often with irregular memory accesses. Current architectures perform poorly for these workloads, as existing prefetching techniques cannot capture the access patterns; applications end up heavily memory-bound a result. Although number exist to explicitly configure prefetcher traversal patterns, gaining significant speedups, they do not generalise beyond their target data structures. Instead, we propose an event-triggered programmable...
Use-after-free vulnerabilities have plagued software written in low-level languages, such as C and C++, becoming one of the most frequent classes exploited bugs. Attackers identify code paths where data is manually freed by programmer, but later incorrectly reused, take advantage reallocating to themselves. They then alter behind program's back, using erroneous reuse gain control application and, potentially, system. While a variety techniques been developed deal with these vulnerabilities,...
The demand for low-power embedded systems requires designers to tune processor parameters avoid excessive energy wastage. Tuning on a per-application or per-application-phase basis allows greater saving in consumption without noticeable degradation performance. On-chip caches often consume significant fraction of the total budget and are therefore prime candidates adaptation. Fixed-configuration must be designed deliver low average memory access times across wide range potential...
SIMD vectors are widely adopted in modern general purpose processors as they can boost performance and energy efficiency for certain applications. Compiler-based automatic vectorization is one approach generating codethat makes efficient use of the units, has benefit avoiding hand development platform-specific optimizations. The Superword-Level Parallelism (SLP) algorithm most well-known implementation when starting from straight-line scalar code, implemented several major compilers....
Many modern data processing and HPC workloads are heavily memory-latency bound. A tempting proposition to solve this is software prefetching, where special non-blocking loads used bring into the cache hierarchy just before being required. However, these difficult insert effectively improve performance, techniques for automatic insertion currently limited. This paper develops a novel compiler pass automatically generate prefetches indirect memory accesses, class of irregular accesses often...
The need to increase performance and power efficiency in modern processors has led a wide adoption of SIMD vector units. All major vendors support instructions the trend is pushing them become wider more powerful. However, writing code that makes efficient use these units hard leads platform-specific implementations. Compiler-based automatic vectorization one solution for this problem. In particular Superword-Level Parallelism (SLP) algorithm primary way automatically generate starting from...
Many modern data processing and HPC workloads are heavily memory-latency bound. A tempting proposition to solve this is software prefetching, where special non-blocking loads used bring into the cache hierarchy just before being required. However, these difficult insert effectively improve performance, techniques for automatic insertion currently limited. This paper develops a novel compiler pass automatically generate prefetches indirect memory accesses, class of irregular accesses often...
The need to increase performance and power efficiency in modern processors has led a wide adoption of SIMD vector units. All major vendors support instructions the trend is pushing them become wider more powerful. However, writing code that makes efficient use these units hard leads platform-specific implementations. Compiler-based automatic vectorization one solution for this problem. In particular Superword-Level Parallelism (SLP) algorithm primary way automatically generate starting from...
This paper presents a novel compiler directed technique to reduce the register pressure and power of file by releasing registers early. The identifies that mil only be read once renames them different logical registers. Upon issuing an instruction with one these as source, processor knows there will no more uses it can release through checkpointing. reduces occupancy our banked file, allowing banks turned off for savings. Our scheme is faster, simpler requires less hardware than recently...