Akinobu Teramoto

ORCID: 0000-0002-4655-9403
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About
Contact & Profiles
Research Areas
  • Semiconductor materials and devices
  • Advancements in Semiconductor Devices and Circuit Design
  • Integrated Circuits and Semiconductor Failure Analysis
  • Copper Interconnects and Reliability
  • Silicon and Solar Cell Technologies
  • Semiconductor materials and interfaces
  • Thin-Film Transistor Technologies
  • Silicon Nanostructures and Photoluminescence
  • Advanced Surface Polishing Techniques
  • Silicon Carbide Semiconductor Technologies
  • GaN-based semiconductor devices and materials
  • Metal and Thin Film Mechanics
  • Plasma Diagnostics and Applications
  • Electron and X-Ray Spectroscopy Techniques
  • Electronic and Structural Properties of Oxides
  • Ga2O3 and related materials
  • ZnO doping and properties
  • Ion-surface interactions and analysis
  • Advanced Memory and Neural Computing
  • Ferroelectric and Negative Capacitance Devices
  • Electrostatic Discharge in Electronics
  • Acoustic Wave Resonator Technologies
  • Ferroelectric and Piezoelectric Materials
  • 3D IC and TSV technologies
  • Advanced ceramic materials synthesis

Hiroshima University
2019-2024

Tohoku University
2013-2022

Tokyo Electron (Japan)
2020-2022

Japan Research Institute
2020

Hatch (Canada)
2005-2017

The University of Tokyo
2008

NTN (Japan)
2007

Mitsubishi Electric (Japan)
1995-2005

Mitsubishi Corporation (United States)
1996-2004

Mitsubishi Group (Japan)
1995-2003

The effect of the Si-SiO/sub 2/ interface microroughness on electron channel mobility n-MOSFETs was investigated. surface controlled by changing mixing ratio NH/sub 4/OH in 4/OH-H/sub 2/O/sub 2/-H/sub 2/O solution RCA cleaning procedure. gate oxide etched, following evaluation electrical characteristics MOS transistors, to measure with scanning tunneling microscopy (STM). As increases, mobility, which can be obtained from current-voltage MOSFET, gets lower. is around 360 cm/sup 2//V-s when...

10.1109/55.116944 article EN IEEE Electron Device Letters 1991-12-01

A static VAr compensator (SVC) using an active filter has been developed that compensates reactive power, harmonic current, negative-phase and voltage fluctuations. The system configuration is described, five types of control scheme for the filter, which are based on practical applications various loads, performance characteristics each type analyzed. shown by simulation to be more effective suppressing arc-furnace flicker than TCR (thyristor-controlled-reactor) SVC.< <ETX...

10.1109/pesc.1988.18259 article EN 2003-01-06

A magnetic material with high permeability and low loss characteristics at frequency is required for miniaturizing electronic components such as antennas. The key factors to keeping are a resonance the suppression of eddy currents. We have fabricated low-loss composite by dispersing Ni <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">78</sub> Fe xmlns:xlink="http://www.w3.org/1999/xlink">22</sub> (permalloy) fine flakes in polymers; thickness was...

10.1109/tmag.2008.2001073 article EN IEEE Transactions on Magnetics 2008-08-27

Current semiconductor technology, the so-called molecule reaction based manufacturing, now faces a very severe standstill due to drastic increase of gate leakage currents and drain currents. Radical manufacturing has been developed completely overcome current by introducing microwave excited high density plasma with low electron temperatures without accompanying charge-up damage.

10.1088/0022-3727/39/1/r01 article EN Journal of Physics D Applied Physics 2005-12-15

Abstract This study investigates the switching characteristics of magnetic tunnel junctions (MTJs) used in spin-transfer-torque magnetoresistive random-access memory. MTJs are expected to exhibit parallel (P) and antiparallel (AP) states, but some an intermediate (IM) state between P AP states at switching. Here we analyze detail size dependence write error rates (WERs) with IM states. The number increases increasing MTJ size. WER is independent occurrence itself causes a writing error.

10.35848/1347-4065/adc26f article EN Japanese Journal of Applied Physics 2025-03-19

In this paper, we demonstrate CMOS characteristics on a Si(110) surface using flattening processes and radical oxidation. A is easily roughened by OH <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-</sup> ions in the cleaning solution compared with Si(100) surface. flat realized combination of processes, which include high-temperature wet oxidation, five-step room-temperature as pregate-oxidation cleaning, does not employ an alkali solution. On...

10.1109/ted.2007.896372 article EN IEEE Transactions on Electron Devices 2007-06-01

Technology to atomically flatten the silicon surface on (100) orientation large-diameter wafer and formation technology of an flat insulator film/silicon interface are developed in this paper. Atomically surfaces composed atomic terraces steps obtained 200-mm-diameter wafers by annealing pure argon ambience at 1200 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">deg</sup> C for 30 min. with various terrace widths step structures observed force...

10.1109/ted.2008.2010591 article EN IEEE Transactions on Electron Devices 2009-01-20

Very thin oxide films with a high electrical insulating performance have been grown by controlling preoxide growth using the ultraclean oxidation method. The current level through is lower than that conventional dry including thicker preoxide. barrier height at silicon-oxide interface for electrons emission from silicon to little decreased as thickness thinner, while drastically decreased. rate of 900 °C governed simple parabolic law even in range 5–20 nm.

10.1063/1.107084 article EN Applied Physics Letters 1992-04-27

High quality SiO 2 /Al O 3 gate stack has been demonstrated for GaN metal–oxide–semiconductor (MOS) transistor. We confirmed that Al could realize a low interface-state density between and GaN, however, the breakdown field was low. By incorporating merits of both , which high large charge-to-breakdown, structure employed in MOS devices. The shows interface state insulator field, charge-to-breakdown. also applied to AlGaN/GaN hybrid heterojunction field-effect transistor (HFET). MOS-HFET...

10.7567/jjap.52.04cf09 article EN Japanese Journal of Applied Physics 2013-03-21

An yttrium oxyfluoride (YOF) protective material was developed for the inner wall of plasma process equipment. Using microwave-excited surface-wave high-density equipment, chemical stability obtained YOF films evaluated by exposure to H2/Ar, N2/Ar, NH3/Ar, O2/Ar, and NF3/Ar plasmas. The film surface stable against these plasmas containing hydrogen, nitrogen, oxygen, fluorine. Especially, fluoridation better than that Y2O3, which is currently widely used as in chambers.

10.1116/1.4975143 article EN Journal of Vacuum Science & Technology A Vacuum Surfaces and Films 2017-01-31

A model is proposed to explain the dependence of substrate hole current in n-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) on applied electric field and oxide thickness. Two types devices were prepared: MOSFETs with gate oxides 67, 86, 131 Å p-channel which thicknesses almost equal those MOSFETs. The carrier-separation technique was used MOSFETs, average energy hot electrons entering silicon obtained. related distribution holes created by emitted from into n+...

10.1063/1.358681 article EN Journal of Applied Physics 1995-04-01

Current silicon technologies are now facing very severe standstill, i.e., the operation speed is strictly limited at a clock rate of about 3.8 GHz due to limitation thinning gate insulator film thickness because its large amount leakage currents through current thermal oxide films. This typical disadvantage has been completely overcome by introducing newly developed radical-reaction-based semiconductor manufacturing instead molecule-reaction-based manufacturing, direct nitridation films such...

10.1109/ted.2007.896391 article EN IEEE Transactions on Electron Devices 2007-06-01

We develop a high-speed method to extract time constants and noise amplitude of random telegraph (RTN). investigate distributions these RTN parameters for more than 270 n- p-MOSFETs clarify spectroscopy traps causing RTN. Most are distributed in an energy range 220 meV, mean times capture/emission measured wide between 10 μs 20 ms.

10.1109/irps.2011.5784503 article EN International Reliability Physics Symposium 2011-04-01

In this study, we focus on the improved device characteristics of fully depleted silicon-on-insulator (FD-SOI) metal–oxide–semiconductor field-effect transistors (MOSFETs) a Si(110) surface using normally off accumulation-mode structures. It is demonstrated that current drivability an FD-SOI n-MOSFET about 1.5 times larger than conventional inversion-mode (110)-oriented surface. Furthermore, it confirmed p-MOSFET fabricated also 3 pMOS formed Si(100)

10.1143/jjap.45.3110 article EN Japanese Journal of Applied Physics 2006-04-01

This paper reports that the low-frequency noise in p-channel MOSFETs fabricated on [110] and (100) crystallographic oriented silicon is related to microroughness of surface. Since conventional RCA cleaning process makes surface rough, especially case orientation, authors developed so-called 5-step room temperature does not use alkaline solution. The combination this new with microwave-excited high-density plasma oxidation for formation gate oxide, instead standard 900/spl deg/C thermal...

10.1109/ted.2006.871188 article EN IEEE Transactions on Electron Devices 2006-04-01

In this paper, we propose an advanced Test Element Group (TEG) which can measure a large number (10 MOSFETs) of electrical characteristics or noise with high accuracy in very short time (0.2 sec/frame). We analyzed fluctuations these statistically using TEG, as the result, confirmed that frequencies Random Telegraph Signal (RTS) appearance and amplitudes RTS become larger scaling-down from statistical analysis. did not find correlation between DC characteristic random is caused by RTS.

10.1109/vlsit.2007.4339696 article EN 2007-06-01

Random Telegraph Noise (RTN) has become one of the most important problems in continuous downscaling CMOS circuitry. We demonstrate RTN reduction by introducing buried channel (BC) MOSFETs and discusse its mechanism. Because larger distance between SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /Si interface, it is more difficult for conduction carriers to be captured emitted from insulator. The effective coulomb blockade radius...

10.1109/irps.2012.6241809 article EN 2022 IEEE International Reliability Physics Symposium (IRPS) 2012-04-01

Abstract The surface roughness of silicon wafer is one the most important issues that degrade characteristics semiconductor devices. importance spatial frequency as an influential parameter has been pointed. In this research, effect on MOSFET was studied using samples with different for frequency. From obtained results, it found a low wavelength affects electron mobility and gate insulating film reliability such E bd , Q SILC.

10.35848/1347-4065/ab918c article EN cc-by Japanese Journal of Applied Physics 2020-05-08

In this paper, we demonstrate newly developed process technology to fabricate complementary metal–oxide–silicon field-effect transistors (CMOSFETs) having atomically flat gate insulator film/silicon interface on (100) orientated silicon surface. They include 1,200 °C ultraclean argon ambient annealing for surface flattening and radical oxidation device isolation, flatness recovery after ion implantation, formation. The fabricated CMOSFET with exhibit very high current drivability such as 923...

10.1143/jjap.48.04c048 article EN Japanese Journal of Applied Physics 2009-04-01

We demonstrate a low temperature flattening method for the 200-mm-diameter (100) orientation silicon wafers. By annealing in ultra pure argon ambient at 850ºC or above, atomically flat surfaces composed of atomic terraces and steps appear uniformly whole 200mm wafer. The width terrace changes with off angle wafer surface. It is found that 0.50º below, only mono-atomic on surface, widths are almost equal to calculation values. Moreover, we have using vertical furnace surface can be flattened...

10.1149/1.3375615 article EN ECS Transactions 2010-04-16

A study of the impact channel direction over effective mobility and 1/f noise in MOSFETs fabricated on (100) (110) silicon-oriented wafers finding its outcome fabrication future nonplanar device structures has been done. We found that, apart from a slight enhancement maximum for p-MOSFETs with along 100 direction, had no effect level performances transistors when they are wafers. This suggests that but already existing CMOS technology is possible by fabricating direction. Regarding wafers,...

10.1109/ted.2010.2047584 article EN IEEE Transactions on Electron Devices 2010-05-26

Using a large-scale array test circuit, both static characteristics and random telegraph noise (RTN) of in-pixel source follower equivalent transistors CMOS image sensor with buried surface channel transistor structures were statistically evaluated under various current body bias conditions. The distribution intensities at operational conditions, correlations between RTN amplitude analyzed. It was found that the has positive correlation subthreshold swing for types transistors.

10.1109/ted.2013.2278980 article EN IEEE Transactions on Electron Devices 2013-08-29

The effects of n-type dopant (P, As) concentration in silicon (100), temperature, and oxidizing species on native oxide growth liquid water are described. phosphorus (P)- arsenic (As)-doped n + -Si surfaces (10 20 cm -3 ) ultrapure exhibits saturation thickness, suggesting a field-assisted mechanism. Oxide thickness was also found n-Si hydrogen peroxide (H 2 O solution or H the presence platinum (Pt) mesh that creates radicals ions. rate increases with an increase temperature.

10.1143/jjap.29.l2392 article EN Japanese Journal of Applied Physics 1990-12-01

Dual shower head microwave-excited plasma etching equipment for separating the plasma-excited region from process has been developed. With aim of realization damage-free etching, carrier activation boron-doped p + -Si is investigated after irradiation. The damage-free-etching mode in which holes do not deactivate was found. Contact are successfully etched using a surface consisting high-speed and mode. consists low-self-bias condition low gas flow rate as compared with For both modes, etcher...

10.1143/jjap.43.1784 article EN Japanese Journal of Applied Physics 2004-04-01

Evaluating the statistical variation of metal–oxide–semiconductor field-effect transistors (MOSFETs) is important for realizing accurate analog circuits and highly large-scale-integration (LSI) devices. In this paper, a new evaluation method electrical characteristics MOSFETs presented. We have developed test circuit understanding local MOSFET in very short time. It demonstrated that large number MOSFETs, about 30,000 are measured time 0.05 s, results useful to develop process technology...

10.1143/jjap.46.2054 article EN Japanese Journal of Applied Physics 2007-04-01
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