Bofan Chen

ORCID: 0000-0002-5790-9667
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About
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Research Areas
  • Radio Frequency Integrated Circuit Design
  • Microwave Engineering and Waveguides
  • Advancements in PLL and VCO Technologies
  • Analog and Mixed-Signal Circuit Design
  • Human Pose and Action Recognition
  • Full-Duplex Wireless Communications
  • Antenna Design and Optimization
  • Diabetic Foot Ulcer Assessment and Management
  • Multimodal Machine Learning Applications
  • CCD and CMOS Imaging Sensors
  • Gyrotron and Vacuum Electronics Research
  • Semiconductor Lasers and Optical Devices
  • Advanced Battery Technologies Research
  • Photonic and Optical Devices
  • Robotics and Sensor-Based Localization
  • Advanced Differential Equations and Dynamical Systems
  • GaN-based semiconductor devices and materials
  • UAV Applications and Optimization
  • Distributed Control Multi-Agent Systems
  • Meromorphic and Entire Functions
  • Holomorphic and Operator Theory
  • Ultra-Wideband Communications Technology
  • Acoustic Wave Resonator Technologies
  • Electromagnetic Compatibility and Noise Suppression
  • Sensor Technology and Measurement Systems

Southeast University
2021-2024

Zhejiang University
2023

National University of Singapore
2023

Fudan University
2022

Class prototype construction and matching are core aspects of few-shot action recognition. Previous methods mainly focus on designing spatiotemporal relation modeling modules or complex temporal alignment algorithms. Despite the promising results, they ignored value class matching, leading to unsatisfactory performance in recognizing similar categories every task. In this paper, we propose GgHM, a new framework with Graph-guided Hybrid Matching. Concretely, learn task-oriented features by...

10.1109/iccv51070.2023.00167 article EN 2021 IEEE/CVF International Conference on Computer Vision (ICCV) 2023-10-01

This paper describes a ultra-wideband (UWB) three-stage cascaded high gain amplifier with low group delay variation for phased-array radar system. The shunt inductor at the input not only provides an electrostatic discharge (ESD) path to ground, but also introduces new notch S11, thus extending matching bandwidth. Staggered tuning of load impedance peaks each stage facilitates balance between flat and variation. output further enhances overall while reinforcing bandwidth stability through...

10.1016/j.mejo.2024.106157 article EN Microelectronics Journal 2024-03-07

A fully integrated 6-15.3 GHz active digital step attenuator (DSA) with 5-bit gain control for phased-array radar system in SMIC 40-nm CMOS technology is presented this brief. Based on a novel current-tuning variable amplifier (VGA)-topology, amplitude over wider band achieved. The main amplification common-source (CS) transistor was designed to operate the linear region larger attenuation range. fabricated DSA exhibits 15.5-dB tuning range 0.5-dB step, constant input and output impedance...

10.1109/tcsii.2024.3375860 article EN IEEE Transactions on Circuits & Systems II Express Briefs 2024-04-01

A fully integrated 6–18 GHz bulk CMOS ultra-wideband (UWB) gain-compensation amplifier for phased-array radar system based on SMIC 40-nm process is presented in this paper. Combined with dual-branch input matching network, three-stage cascaded amplification and both the inductive series- shunt-peaking techniques, gain 3-dB bandwidth (BW) further extended. The fabricated UWB achieves a flat of 8.7–13.3 dB an averaged noise figure (NF) 5.75 return loss better than −15.1 dB. Measured 1-dB...

10.1016/j.mejo.2023.105869 article EN Microelectronics Journal 2023-06-13

The unmanned air-ground vehicle system has been successfully applied in civil and military domains. Collaborative vision-based target geolocation with this can provide an enduring accurate estimate of moving state. Traditional decentralized information filter (DIF) treated each platform the identically. In fact, observation capabilities aerial ground typically differ from other due to different configurations changing sensor noises. Without considering these differences, resources cannot be...

10.1109/tsmc.2023.3297597 article EN IEEE Transactions on Systems Man and Cybernetics Systems 2023-08-08

10.1109/tcsii.2024.3432621 article EN IEEE Transactions on Circuits & Systems II Express Briefs 2024-07-23

Class prototype construction and matching are core aspects of few-shot action recognition. Previous methods mainly focus on designing spatiotemporal relation modeling modules or complex temporal alignment algorithms. Despite the promising results, they ignored value class matching, leading to unsatisfactory performance in recognizing similar categories every task. In this paper, we propose GgHM, a new framework with Graph-guided Hybrid Matching. Concretely, learn task-oriented features by...

10.48550/arxiv.2308.09346 preprint EN cc-by-nc-nd arXiv (Cornell University) 2023-01-01

A 6–18-GHz ultrawideband vector-sum phase shifter (PS) with 6-bit digital control for phased-array system in SMIC 40-nm CMOS process is presented this article. Combination of two inserted balanced buffers, elaborately optimized RC third-order I/Q signals generator, and novel complementary current source compensation technique contributes to the low rms gain error. The fabricated PS exhibits a full-360° tuning range 5.625° step good matching characteristics. measured error are,...

10.1109/tvlsi.2023.3331508 article EN IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2023-11-17

In this paper, based on TSMC 22nm CMOS process, a Charge Pump with working frequency of 50MHz is designed. order to further expand the output voltage range current matching CP when charging and discharging, structure low differential mirror technology was proposed. Rail-to-rail operational amplifier used clamp improve accuracy charge discharge CP.

10.1109/icicm54364.2021.9660364 article EN 2022 7th International Conference on Integrated Circuits and Microsystems (ICICM) 2021-10-22

This paper presents a four-core LC-VCO array in 55 nm CMOS technology. Based on the multi-core VCO technology and switched capacitor technology, tuning range is expanded, phase noise optimization wide achieved based second harmonic filtering Q value degeneration as well of switching transistors. The proposed array, occupying chip area 1.65 × 1.44 mm2, realizes measured oscillation frequency about 3.7−10 GHz with −127.5~−116.08 dBc/Hz at 1 MHz offset, achieves an output power 2.69 dBm from...

10.3390/electronics11121897 article EN Electronics 2022-06-16

Abstract This article will first introduce the conception of complex numbers and then deal with some famous results in numbers. In beginning, we prove Cauchy-Goursat theorem calculate integral along a closed path domain on which given function is analytic. We want to check relation between being analytic, having primitive, its equals zero. conclusion, for analytic simply connected domain, any Using this can residue Cauchy formula. To existence uniqueness Laurent expansion, decomposition by...

10.1088/1742-6596/2381/1/012056 article EN Journal of Physics Conference Series 2022-12-01

This paper presents a compact 0.0625–4 GHz fractional-N frequency synthesizer with quadrature phase output for software-defined radios (SDRs). Four voltage controlled oscillators (VCOs) and six cascaded dividers are used wideband operation. Second harmonic filtering high noise suppression techniques applied in VCO optimization. Inverter switch cascade buffers combined channel selection enhancement amplitude improvement. A large dynamic range minimum current variation mismatch is achieved by...

10.1016/j.mejo.2021.105334 article EN Microelectronics Journal 2021-12-03

This paper presents a 6–18 GHz 7-bit digitally controlled active variable attenuator with phase-invariant technique in 40-nm CMOS technology for wideband phased-array applications. A current-steering structure is implemented the attenuation tuning while proposed to reduce phase variation between different modes. In addition, inductive peaking utilized bandwidth extension and gain flatness. The exhibits simulated range of 15.5 dB 0.5 steps, Root-Mean-Square (RMS) amplitude error within are...

10.1109/ccpis59145.2023.10292079 article EN 2023-09-01

This paper presents a ultra-wideband (UWB) amplifier with three cascaded stages to expand operational bandwidth. The shunt inductor at the input provides an electrostatic discharge (ESD) protection path ground. Implemented in SMIC 40nm CMOS technology, proposed topology achieves good impedance matching, flat gain of 17.8–19.9dB and low group delay (GD) variations 169.0 ± 61.4 ps over 6-18 GHz, simultaneously. consumes 188.1 mW totally under 2.5-V supply output 1 dB compression point...

10.1109/icicm59499.2023.10365936 article EN 2022 7th International Conference on Integrated Circuits and Microsystems (ICICM) 2023-10-20

A 5th-order Chebyshev-I active-RC analog low-pass filter (LPF) with programmable cutoff frequency (f<inf>0</inf>) was fabricated in a 22nm ultra-low-leakage CMOS process. The proposed is targeted to application scenarios such as low-voltage and low-power wireless communication systems different base-band signal bandwidths. reconfiguration of the realized novel way by switched-resistors proportional resistance values. two-stage fully differential operational amplifier (op-amp) feed-forward...

10.1109/icspcs53099.2021.9660299 article EN 2021-12-13
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