A5075004901- Semiconductor materials and devices
- Advancements in Semiconductor Devices and Circuit Design
- Integrated Circuits and Semiconductor Failure Analysis
- Silicon Carbide Semiconductor Technologies
- Nanowire Synthesis and Applications
- Advanced Memory and Neural Computing
- Ferroelectric and Negative Capacitance Devices
- Thin-Film Transistor Technologies
- Quantum and electron transport phenomena
- Semiconductor materials and interfaces
- Silicon and Solar Cell Technologies
- Photonic and Optical Devices
- Non-Invasive Vital Sign Monitoring
- Low-power high-performance VLSI design
- Photonic Crystals and Applications
- Heart Rate Variability and Autonomic Control
- ZnO doping and properties
- Semiconductor Quantum Structures and Devices
- Analog and Mixed-Signal Circuit Design
- Radio Frequency Integrated Circuit Design
- Electronic and Structural Properties of Oxides
- Electrostatic Discharge in Electronics
- Silicon Nanostructures and Photoluminescence
- ECG Monitoring and Analysis
- Advanced Chemical Sensor Technologies
Kansai University
2015-2025
Association of Canadian Archivists
2023
Ryukoku University
2023
Kindai University
2023
Warsaw University of Technology
2023
Osaka Institute of Technology
2023
Software Research Associates (Japan)
2021
Osaka City University
2018-2019
Suita Municipal Hospital
2014
NTT Basic Research Laboratories
1989-2003
A theoretical description is given of the dependence threshold voltage, V/sub TH/, SOI MOSFETs on a wide range to top silicon layer thickness, t/sub s/, using both classical and quantum-mechanical methods. The effects become remarkable below critical thickness raise TH/ with decreasing s/. method cannot be applied in such thin s/ region, since classically obtained decreases monotonously even thickness. As result, curve as function can divided into two regions boundary at above that...
The Telescope Array observatory utilizes fluorescence detectors and surface to observe air showers produced by ultra high energy cosmic rays in the Earth's atmosphere. Cosmic ray events observed this way are termed hybrid data. depth of shower maximum is related mass primary particle that generates shower. This paper reports on maxima data collected over 8.5 years using Black Rock Mesa Long Ridge conjunction with array detectors. We compare means standard deviations $X_{\mathrm{max}}$...
A 0.1- mu m-gate CMOS/SIMOX is fabricated using high-quality SIMOX substrates with a sub-100-nm-thick buried oxide layer. In addition, 0.085- nMOSFETs/SIMOX and pMOSFETs/SIMOX 8-nm-thick silicon active layers have been fabricated. The prospects for improving the performance of devices are discussed in detail.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
In this article, we report an investigation of the effects variation in temperature range 300-450 K on analog performance and harmonic distortion (HD) characteristics a Ge-source tunnel FET (TFET) using numerical device simulator. Variation parameters, such as transconductance, intrinsic gain, output resistance, is found to be small for large temperature. HD parameters are also almost insensitive over good range.
This paper demonstrates mesoscopic scale nMOSFET's fabricated by Separation IMplanted OXygen (SIMOX) technology on a trial basis and describes their explicit quantum-mechanical transport phenomena: enhanced threshold voltage in an extremely thin silicon-on-insulator (SOI) structure short-channel effect at room temperature as well weak interference (WI) relatively high temperatures (/spl sim/40 K), which are characterized specifically SOI devices.
A lateral, unidirectional, bipolar-type insulated-gate transistor (Lubistor) is newly proposed. It has three features: a p+-n (or p)-n+ structure, an insulated gate on the n(or p) region, and thickness of region approximately equal to or less than effective Debye length. shown that Lubistor triodelike current-voltage characteristics, characteristic curve shifts continuously toward high anode-to-cathode bias along voltage axis when gate-to-cathode enhances majority-carrier concentration in...
An extremely low-power CMOS/SIMOX divide-by-128/129 dual-modulus prescaler that operates at up to 1 GHz and dissipates 0.9 mW a supply voltage of V is presented. The capable 2-GHz performance with dissipation 7.2 2 V. This superior primarily achieved by using an advanced ultrathin-film process technology combined circuit configuration uses divide-by-2/3 synchronous counter. Using these same technologies, single-chip CMOS phase-locked-loop (PLL) LSI the developed was fabricated. It can...
Four types of frequency dividers were fabricated on SIMOX/SOI (separation by implanted oxygen/silicon insulator) substrates. A novel circuit among these four circuits showed the highest operation 1.2 GHz under 1-V supply voltage, with gate lengths 0.15 and 0.1 mu m. Power consumption was no more than 50 62 W for both 0.15- 0.1- m designs, respectively.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
This paper puts forward an advanced consideration on the design of scaled multiple-gate FET (MuGFET); aspect ratio (RSUBh/w/SUB) fin height (h) to width (w) MuGFET is considered with aid 3-D device simulations. Since any change in must consider trade-off between drivability and short-channel effects, it shown that optimization essential designing MuGFET's. It clearly seen triple-gate (TG) superior conventional FinFET from viewpoints effects as was be expected. can concluded guideline w <...
This letter proposes a new device structure which is called the "partial-ground-plane (PGP) silicon-on-insulator (SOI) MOSFET." The PGP SOI MOSFET minimizes short-channel effect (SCE) compared to conventional single-gate (SG) because gate-induced field in layer held high by region. results lower stand-by leakage current. also shows much better switching performance and extremely analog of its smaller parasitic capacitance ground-plane (GP) device. Thus, it shown that promising candidate for...
A 0.1- mu m-gate CMOS/SIMOX (separation by implanted oxygen) has been successfully fabricated using high quality SIMOX substrates and an advanced design concept for the subquarter-micron region based on a simple device model. In addition, both 85-nm-gate n- p-MOSFETs/SIMOX with 8-nm-thick silicon active layer have realized. High parasitic resistance in source drain regions of tends to increase propagation delay time. However, devices time as low 10 ps can be obtained reducing resistance.<...
This paper describes two-dimensionally confined carrier injection phenomena in thin-SOI insulated-gate pn-junction devices fabricated on SIMOX substrates. At 28 K conductance shows step-like anomalies due to the manifestation of a two-dimensional subband system an 8-nm-thick-SOI structure at low gate bias. Conductance oscillation-like feature high bias because mode change. These effects are examined by theoretical simulations based quantum mechanics.
A simplified experimental analysis of the body-contact effect and its impact on drain current reduction is carried out to clarify relevant parameters for MOSFET/SOI design. In experiments, body contacts in source are distributed a mosaic configuration. The empirical relationship between number obtained. suggests that there must be sufficient suppress kink avoid current.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
The pseudo-MOS transistor technique is useful for quick and accurate characterization of as-fabricated silicon-on-insulator wafers. sample size probe-pressure effects on the drain current are revisited. It demonstrated that geometrical factor significantly affected by probe-to-edge distance probe pressure. correct factor, reflecting silicon island size, pressure effects, extracted from systematic experimental results used to determine actual carrier mobility.
The physical basis and the limitation for universal mobility behavior of fully depleted silicon-on-insulator (SOI) metal–oxide–semiconductor Si inversion layers are shown by means an analysis electronic states (potential profile, subband structure, electron density distribution). As long as top layer thickness is larger than much higher impurity concentration in region, it proved that SOI region equivalent to those a certain bulk region. In this context, definition effective vertical...
A deep submicrometer gate MOSFET with fully depleted channel was fabricated using ultrathin Si film on SIMOX (separation by implanted oxygen) substrates. Ultrathin films thicknesses down to 30 nm are shown be effective in reduction of the short-channel effect. Thus, MOSFETs steep subthreshold slopes and threshold voltages insensitive drain voltage were realized. The propagation delay a CMOS inverter an substrate measured 51-stage ring oscillator configuration, 0.25- mu m built...
This paper describes a high-speed buried channel MOSFET dielectrically isolated from the substrate through use of oxygen implantation technology. An implanted silicon dioxide layer is formed just beneath surface. n-type epitaxial grown on remaining thin single-crystal at Then, MOSFET's are layer. The interface between SiO <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> and upper abrupt, charge density 6.9 × 10 <sup...
We spectroscopically investigate the impact of alcohol intake on photoplethysmogram (PPG) signal and confirm that can be discerned by optoelectronic sensors. This paper focuses specific spectra PPG demonstrates importance observing harmonics ratio signal. In contrast to past studies, it is strongly suggested best light source for detecting a green-LED. An analysis time evolution harmonic shows includes important information from which despite complexity involved. assessment supported...
Abstract In this paper, a novel device structure for gate-on-germanium source (GoGeS) tunnel field-effect transistor (TFET) on bulk silicon substrate is proposed sub-0.5-V operation. Tunneling in line with the gate electric field, which increases effective tunneling area and, hence, ON-state current ( I ON ) achieved by constructing its germanium region. To improve subthreshold swing SS ), lateral carrier eliminated carefully designing structure. The use of small gate-to-channel overlap...
This paper describes an explicit manifestation of quantum-mechanical influences on the short channel effects (SCE) in threshold voltage ultra-thin buried-channel MOSFET/SIMOX devices. The theoretical model predicts abnormal quantum mechanical SCE (QSCE) extremely thin SOI layer. It also that QSCE becomes much salient at low temperatures, which is examined quantitatively by experiments.