A5101955679- Semiconductor materials and devices
- Integrated Circuits and Semiconductor Failure Analysis
- Advancements in Semiconductor Devices and Circuit Design
- Advanced Semiconductor Detectors and Materials
- Semiconductor Quantum Structures and Devices
- Additive Manufacturing Materials and Processes
- High Entropy Alloys Studies
- Copper Interconnects and Reliability
- Inorganic Fluorides and Related Compounds
- Metal and Thin Film Mechanics
- Fusion materials and technologies
- Chalcogenide Semiconductor Thin Films
- Solid-state spectroscopy and crystallography
- Aluminum Alloys Composites Properties
- Electronic Packaging and Soldering Technologies
- Electrostatic Discharge in Electronics
- Additive Manufacturing and 3D Printing Technologies
- Ferroelectric and Piezoelectric Materials
- Phase-change materials and chalcogenides
- Advanced Welding Techniques Analysis
- Semiconductor materials and interfaces
- Material Science and Thermodynamics
- Microwave Dielectric Ceramics Synthesis
- Advanced materials and composites
- Acoustic Wave Resonator Technologies
University of North Texas
2022-2024
University of New Mexico
2021-2023
Institute of Electrical and Electronics Engineers
2017-2021
Massachusetts Institute of Technology
2019-2021
Nagoya Institute of Technology
2019-2021
Institut für Mikroelektronik Stuttgart
2021
National Yang Ming Chiao Tung University
2021
Ames Research Center
2020
Western Digital (Japan)
2020
Nanyang Technological University
2020
Current work explored solid-state additive manufacturing of AZ31B-Mg alloy using friction stir deposition. Samples with relative densities ≥ 99.4% were additively produced. Spatial and temporal evolution temperature during deposition was predicted multi-layer computational process model. Microstructural in the fabricated samples examined electron back scatter diffraction high-resolution transmission microscopy. Mechanical properties evaluated by non-destructive effective bulk modulus...
Additive friction stir deposition has been proposed as a disruptive manufacturing process; involving complex thermo-mechanical mechanisms during multilayer material deposition. The current efforts have attempted to develop FEM based pseudo-mechanical thermal model accounting for heat generation due and plastic dissipation additive primary motivation development of the was seek an understanding their impact on microstructural evolution predicted temperature–time profiles agreed well with...
A physical model has been developed which complies with the experimental observation on failure mechanism of ultrathin gate oxide breakdown during constant voltage stress. Dynamic equilibrium needs to be established between percolation conductive path and dielectric induced epitaxy (DBIE) formation transient. The is capable linking model, soft breakdown, hard DBIE growth for a variety stress conditions thickness without involving new empirical parameters.
Additive manufacturing offers flexibility for intricate components and also allows precise control over the microstructure. This review paper explores current state of art in additive techniques Alnico permanent magnets, emphasizing notable advantages challenges associated with this innovative approach. Both LPBF L-DED processes have demonstrated promising results fabricating magnetic properties comparable conventionally processed samples. The optimization process parameters successfully...
Electromigration in the lower metal (M1) and upper (M2) of Cu dual-damascene interconnections has been studied. The failure times M2 test structures are significantly longer than those identical M1 structures. It is proposed that this asymmetry result a difference location void formation growth, which believed to be related ease electromigration-induced nucleation growth at Cu/Si3N4 interface. Asymmetric via reliability therefore an intrinsic characteristic current interconnect technology.
The physical evidence describing the structural deformation at failure site of soft breakdowns (SBDs) in 33-/spl Aring/ and 25-/spl ultrathin gate oxide narrow MOSFETs is reported. A "hillock" type epitaxial Si spot with size ranging from 2 to 100 nm associated gate-oxide breakdown always found vicinity its formation depends strongly on stress polarity. This believed be induced by event this phenomenon can named as polarity-dependent dielectric breakdown-induced epitaxy (DBIE).
Numerous failure mechanisms associated with hard breakdowns (HBD) in ultrathin gate oxides were physically studied high-resolution transmission electron microscope (TEM). Migration of silicide from silicided and source/drain regions, abnormal growth dielectric-breakdown-induced epitaxy (DBIE), poly-Si meltdown recrystallization, severe damage Si substrate, total substrate the entire transistor are among common microstructural damages observed metal-oxide-semiconductor field-effect...