With rapid development of micro-processors, off-chip memory access becomes a system bottleneck. DRAM, main in most computers, has concentrated only on capacity and bandwidth for decades to achieve high performance computing. However, DRAM latency should also be considered keep the trend multi-core era. Therefore, we propose NUAT which is new controller focusing reducing without any modification existing structure. We exploit DRAM's intrinsic phenomenon: electric charge variation cell...

Several previous works have changed DRAM bank structure to reduce memory access latency and shown performance improvement. However, changes in the area-optimized can incur large area-overhead. To solve this problem, we propose Multiple Clone Row (MCR-DRAM), which uses existing without any modification.

As DRAM data bandwidth increases, tremendous energy is dissipated in the bus. To reduce consumed bus, interfaces with asymmetric termination, such as Pseudo Open Drain (POD) and Low Voltage Swing Terminated Logic (LVSTL), have been adopted modern DRAMs. In using amount of termination proportional to hamming weight words. this work, we propose Bitwise Difference Encoding (BD-Encoding), which decreases words, leading a reduction consumption Since smaller words also reduces switching activity,...

As DRAM data bandwidth increases, tremendous energy is dissipated in the bus. To reduce consumed bus, interfaces with symmetric termination, such as Pseudo Open Drain (POD) and Low Voltage Swing Terminated Logic (LVSTL), have been adopted modern DRAMs. In using asymmetric amount of termination proportional to hamming weight words. this work, we propose Bitwise Difference Encoding (BD-Encoding), which decreases words, leading a reduction consumption Since smaller words also reduces switching...

It is widely known that relatively long DRAM latency forms a bottleneck in computing systems. However, vendors are strongly reluctant to decrease due the additional manufacturing cost. Therefore, we set our goal reduce without any modification existing structure. To accomplish goal, focus on an intrinsic phenomenon DRAM: electric charge variation cell capacitors. Then, draw two key insights: i) row-access of row function elapsed time from when was last refreshed, and ii) also remaining until...

The relatively high latency of DRAM is mostly caused by the long row-activation time which in fact consists sensing and restoring time. Memory controllers cannot distinguish between them since they are performed consecutively a single command. If these two steps separated, can be delayed until access uncongested. Hence, we propose Quick-Access (Q-DRAM) discriminates restoring. Our approach to allow destructive (i.e., only without command) using per-bank multiple row-buffers. We call...

As the number of datasets processed in computing systems has increased recent years, there is growing demand for high capacity main memory subsystems. However, further increases conventional DRAM-based have stalled due to scaling limitations. Recent studies shown that PCM, which can provide greater than DRAM, emerging as a candidate memory. PCM suffers from problems related thermal mechanisms employed storing data. The Write Disturbance (WD) phenomenon occurs when severely damage data...

Initializing memory with zero data is essential for safe management. However, initializing a large area slows down the system significantly. The most likely cause initialization to slow limited DRAM method. At present, only way initialize execute multiple WRITE commands. command because of its small granularity and bus occupancy. In this brief, we propose an efficient in-DRAM method inspired by internal structure operation DRAM. proposed method, called row reset, uses buffer out single at...

As the DRAM cell size continues to shrink, proportion of leaky cells is increasing. a result, prior approaches, called retention aware refresh, which skip unnecessary refresh operations for non-leaky cells, are unable as many before. The large granularity mechanism makes this problem more serious. Specifically, even when there only small number in particular group, that group classified group. Because that, also belong refreshed at an unnecessarily frequent rate. Since larger, inefficiency...

As DRAM scaling becomes ever more difficult, Phase Change Memory (PCM) is attracting attention as a new memory or storage class memory. Unfortunately, PCM cell data can be changed by frequently writing ‘0’ to adjacent cells. This phenomenon called Write Disturbance (WD). To mitigate WD errors with low performance overhead, we propose Detection Cell (DC-PCM). In the DC-PCM, additional cells Cells (DC) are allocated memory-line pre-detect errors. For pre-detection, schemes that give DCs higher...

Several previous works have changed DRAM bank structure to reduce memory access latency and shown performance improvement. However, changes in the area-optimized can incur large area-overhead. To solve this problem, we propose Multiple Clone Row (MCR-DRAM), which uses existing without any modification. Our key idea is (MCR), multiple rows are simultaneously turned on or off consist of a logically single row. MCR provides two advantages enable our low-latency mechanisms (Early-Access,...

DRAM systems are hierarchically organized: Channel-Rank-Bank. A channel is connected to multiple ranks, and each rank has banks. This hierarchical structure facilitates creating parallelisms in DRAM. The current architecture supports bank-level parallelism; as many rows banks can be moved simultaneously at bank-level. However, rank-level parallelism not supported. For this reason, only one column accessed a time, although its own data bus that carry column. Namely, operations do exploit the...

DDR4 SDRAM introduced a new hierarchy in DRAM organization: bank-group (BG). The main purpose of BG is to increase I/O bandwidth without growing DRAM-internal bus-width. We, however, found that other benefits can be derived from the hierarchy. To achieve benefits, we propose architecture using BG-hierarchy, leading creation BG-Level Parallelism (BGLP). By exploiting BGLP, overall parallelism grows operations. We also argue BGLP feasible solution cost-sensitive industry because additional...

Current computer systems require large memory capacities to manage the tremendous volume of datasets. A DRAM cell consists a transistor and capacitor, their size has direct impact on density. While technology scaling can provide higher density, this benefit comes at expense low drivability, due increase in series resistance smaller transistor, which slows process restoring charge cells. operations recovery processes destructive nature Among such operations, write most difficulty meeting...