A5043011026- VLSI and FPGA Design Techniques
- Metaheuristic Optimization Algorithms Research
- VLSI and Analog Circuit Testing
- Advanced Memory and Neural Computing
- Low-power high-performance VLSI design
- Advancements in Semiconductor Devices and Circuit Design
- Ferroelectric and Negative Capacitance Devices
- Image Enhancement Techniques
- Advanced Optical Network Technologies
- Software Engineering Research
- Photonic and Optical Devices
- Advanced Multi-Objective Optimization Algorithms
- Visual Attention and Saliency Detection
- Optical Network Technologies
- Quantum-Dot Cellular Automata
- DNA and Biological Computing
- Industrial Technology and Control Systems
- Remote-Sensing Image Classification
- Infrared Target Detection Methodologies
- Remote Sensing and Land Use
- Software Reliability and Analysis Research
- Video Surveillance and Tracking Methods
- Embedded Systems Design Techniques
- Radiation Effects in Electronics
- Software Testing and Debugging Techniques
Tongji University
2023-2025
Hebei Agricultural University
2022-2023
Area and reliability optimization have become the primary constraints in circuits logic synthesis. To address increasing area transient fault susceptibility combinational circuits, we propose a high-dimensional genetic algorithm (HGA). HGA adopts an evolutionary scheme based on ternary tree, uses adaptive crossover operator flight to jump out of local optimum. Moreover, HGA, method (AROM) for mixed polarity Reed-Muller which searches best with minimum soft error rate. The experimental...
Identifying reliability high-correlated gates (HRCGs) is vital for fault location and exclusion, especially cascading faults. By executing a linear fit based on the results of circuit's evaluation calibrating function using regression residual analysis, this brief first proves existence HRCGs. A time-series-oriented PCC model then introduced to quantify gates' correlation (GRC) identify all HRCGs in circuit. Circuit-correlated primary outputs sequential circuit-correlated flip-flops were...
With the emergence of multicore architecture and increase chip operating frequency, power optimization has become a key step circuit logic synthesis. Aiming at XNOR/OR circuits, with goal minimizing power, construct optimal polarity fixed-polarity Reed–Muller (FPRM) circuits scheme. However, for FPRM is multipeak combinatorial problem, we first propose metaheuristic algorithm (MOA), which includes global exploration optimizer, local deep exploitation initial population uses proposed...
Area optimization is one of the most important contents circuits logic synthesis. The smaller area has stronger testability and lower cost. However, searching for a circuit with smallest in large-scale space polarity combinatorial problem. existing approaches are inefficient do not consider time In this paper, we propose multi-strategy wolf pack algorithm (MWPA) to solve high-dimension problems. MWPA performs global search based on proposed exploration strategy, extends Levy flight local...
The identification of reliability-critical input vectors (RCIVs) is vital in the assessment and prediction reliability boundaries for logic circuits. This article introduces an approach grounded association rule analysis (ARA) to swiftly efficiently identify RCIVs both combinational sequential utilization ARA model validating circuit's associated primary inputs enhances accuracy while simultaneously reducing complexity identification. Orienting generation new samples with expedites process....
Power optimization can reduce heat dissipation costs and has become an important step of circuit logic synthesis. Because the power for mixed polarity Reed–Muller (MPRM) circuits is a combinatorial problem, in this paper, we first propose multilevel adaptive memetic algorithm (MAMA), which includes global exploration optimizer, local heuristic initial population optimizer. We use proposed differential evolution optimization, simulated annealing data matching to make evolve. Moreover, based...