A5042073861- Analog and Mixed-Signal Circuit Design
- CCD and CMOS Imaging Sensors
- Advancements in PLL and VCO Technologies
- Advancements in Semiconductor Devices and Circuit Design
- Radio Frequency Integrated Circuit Design
- Low-power high-performance VLSI design
- Radiation Effects in Electronics
- Acoustic Wave Resonator Technologies
- Microwave Engineering and Waveguides
- Particle Detector Development and Performance
- Semiconductor materials and devices
- Real-time simulation and control systems
- VLSI and Analog Circuit Testing
- Electrostatic Discharge in Electronics
- Microwave and Dielectric Measurement Techniques
- Wireless Body Area Networks
- Neuroscience and Neural Engineering
- Radiation Detection and Scintillator Technologies
- Advanced Memory and Neural Computing
University of Houston
2016-2023
Guizhou Electric Power Design and Research Institute
2015
This paper presents a backend machine learning-based nonlinearity calibration scheme for coarse-fine two stage SAR-TDC hybrid ADC. Different from conventional approaches, the avoids on-chip pseudonumber (PN) generator or complex, specific matrix operations in digital domain process. The utilizes two-layer neural network to extract and compensate bit-weight error caused by circuit nonlinearities such as inter-stage gain time-to-digital converter (TDC) delay cell mismatch. uses ADC DNL INL...
This article reports a power-efficient 8× time-interleaved (TI) 2.4-GS/s 10-bit successive-approximation-register (SAR) analog-to-digital converter (ADC). To optimize the circuit design in terms of power efficiency and conversion rate, several enhancement techniques are presented. First, pre-defined bypass window, introduced by customized non-binary DAC, is used to modestly reduce consumption. Several cycles skipped as input signal falls within window. Second, enhance operation speed, two...
This letter presents a partially interleaved 1-GS/s 8-bit two-step SAR ADC for low-power operations. A fast noise-reduction technique is proposed to increase the power efficiency without significant degradation of conversion rate. modified StrongARM latch adopted further reduce comparator noise. calibration procedure runs in background address nonuniform offsets and interstage gain error. Fabricated 28-nm FDSOI process, prototype achieves an SNDR 46.65 dB at Nyquist with consumption 2.1 mW,...
This article presents a 5-GS/s 6-bit flash analog-to-digital converter (ADC) in 28-nm fully depleted silicon-on-insulator (FDSOI) CMOS process. The ADC jointly employs partially active second-stage comparison and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2\times $ </tex-math></inline-formula> time-domain latch interpolation (TDI) to reduce power consumption avoid extensive calibrations. To enhance...
This paper presents a 6-bit 20 GS/s 2-way time-interleaved (TI) flash analog-to-digital converter (ADC) in 28-nm FDSOI CMOS technology. Leveraging threshold voltage control via back-gate bias FDSOI, an automatic comparator offset calibration scheme is developed, which does not require extra transistor pairs or capacitive loads signal path, thus avoiding speed degradation. To alleviate channel mismatch-induced errors highly interleaved structure while maintaining reasonable power efficiency,...
This paper presents a 12.5 Gbps serial link transmitter application-specific integrated circuit (ASIC) designed in 65-nm CMOS technology. The ASIC mainly includes an LC-VCO phase-locked-loop (PLL), 16:1 serializer and CML driver. Simulation results show that the PLL achieves 7-to-14 GHz frequency tuning range RMS jitter of 0.4 pS. has deterministic 9 pS programmable output swing from 200 mV to 1.0 V. consumes 39.6 mW 73 1.2 V power supply, respectively.
This paper presents a 14-bit 2.5 GS/s current-steering digital-to-analog converter (DAC) in 65 nm CMOS. Small transistors are utilized this design to reduce the 3rd-order harmonic distortion caused by finite output impedance. However, adoption of small increases 2nd-order and degrades spurious-free dynamic range (SFDR). Hence digital pre-distortion (DPD) scheme is proposed for cancellation. In addition, techniques including element matching (DEM), double-data-rate (DDR) quad switch always-on...
This paper presents a high-speed and power-efficient successive-approximation-register (SAR) analog-to-digital converter (ADC). A dual-DAC architecture is proposed to enhance the conversion rate by decreasing worst-case logic delay thus time needed for each cycle. 1-bit redundancy introduced absorb decision errors caused mismatch between two DACs relax DAC settling requirement. In addition, an addition-only digital error correction technique utilized convert non-binary codes into binary...
In this paper, we present a dual-channel serializer ASIC, LOCx2, and its pin-compatible backup, LOCx2-130, for detector front-end readout. LOCx2 is fabricated in 0.25-μm Silicon-on-Sapphire CMOS process each channel operates at 5.12 Gbps, while LOCx2-130 130-nm bulk 4.8 Gbps. The power consumption the transmission latency are 900 mW 27 ns corresponding simulation result of 386 38 ns, respectively.
This paper presents a receiver front-end circuit for wideband high-frequency ultrasound transducer applications. The front end consists of three main blocks, low noise amplifier (LNA), variable gain (VGA) and biquad pass filter (LPF). is specifically designed polyvinylidene fluoride (PVDF) imaging with typical signal bandwidth 10–60 MHz. To achieve both figure (NF) good impedance matching (S11) performance, nonlinearity canceling technique utilized in the LNA. 0.18 µm CMOS technology....
This paper presents a successive-approximation-register (SAR)-assisted time-interleaved digital-slope analog-to-digital converter (ADC), which takes advantage of both moderate conversion speed the SAR ADC and low noise ADC. A coarse is pipelined with 4 channels fine through passive residue transfer for speed, precision power optimization. charge sharing-based implementation eliminates need power-consuming on-chip reference buffers. compact bootstrapped switch-based chopper proposed to...
This paper presents a simultaneous noise and distortion canceling low amplifier (LNA) for high-frequency ultrasound imaging applications. A feedforward technique is developed to achieve both figure (NF) good input impedance matching (S <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">11</sub> ). The LNA also exploits the complementary characteristics of NMOS PMOS transistors cancel second-order harmonic linearity enhancement. proposed designed in...
This paper presents a current reuse wideband complementary noise and distortion canceling low-noise amplifier (LNA) for high-frequency ultrasound imaging applications. A single-ended current-reuse LNA structure with low-voltage power supply is utilized to achieve low consumption. The employs shunt-feedback feedforward technique accomplish both figure (NF) impedance matching. CMOS topology also exploited cancel the even-order harmonics enhance linearity. designed 30-120 MHz systems,...
This paper presents a low-power silicon photomultiplier (SiPM) readout front-end with on-chip fast pulse generation and successive-approximation-register (SAR) ADC. The mainly consists of current buffer an C-R high pass filter (HPF), charge integrator, discriminator, 10-bit SAR current-mode offers low input impedance thus achieving bandwidth. HPF shortens the width SiPM's long-tailed single photo-electron (SPE) response to generate signal, which allows discriminator suppress uncertainty...
This paper presents an automatic comparator offset calibration scheme for designing high-speed flash analog-to-digital data converters (ADCs). It leverages the threshold voltage control capability via back-gate in FDSOI CMOS technology and thus does not require extra transistor pairs or capacitive loads, avoiding speed degradation. An approach employing a successive approximation algorithm (SAA) is also developed. The along with circuit are designed 28-nm process. Simulation results show...
This letter presents a partially interleaved 1-GS/s 8-bit two-step SAR ADC for low-power operations. A fast noise-reduction technique is proposed to increase the power efficiency without significant degradation of conversion rate. modified StrongARM latch adopted further reduce comparator noise. calibration procedure runs in background address nonuniform offsets and interstage gain error. Fabricated 28-nm FDSOI process, prototype achieves an SNDR 46.65 dB at Nyquist with consumption 2.1 mW,...
This paper presents a 500 MS/s 10-bit single-channel SAR ADC with reconfigurable double-rate comparator for enhanced operation speed. The proposed effectively eliminates the delay caused by reset from critical path while consuming less power and reducing clock frequency half. A test chip is fabricated in 28 nm FDSOI technology. Clocked at MS/s, achieves SNDR of 52.7 dB SFDR 62.49 Nyquist consumption 1.18 mW, showing Walden FOM 6.7 fJ/conv.-step.
A radiation-tolerant delay locked loop (DLL) for DDR2 memory interface is presented. The DLL adjusts clock phase by a coarse tuning using multiplexer-based digitally controlled line (DCDL) and fine interpolator (PI). To protect the sensitive nodes from single event effect (SEE), thermometer coding with bubble correction triple modular redundancy (TMR) techniques are adopted. In addition, duty cycle corrector (DCC) characteristic developed. Designed in 0.13 μm CMOS technology, achieves...
This paper presents a 10-bit 250-MS/s time-interleaved pipelined analog-to-digital data converter (ADC). A distributed clocking scheme is developed to eliminate timing skew between channels without introducing load capacitance the driving buffer of ADC. The channel offset and gain mismatch errors are calibrated in digital domain. In addition, switch-embedded opamp-sharing technique reduce ADC power consumption memory effect. simulated SNDR SFDR 61.84 dB 78.2 dB, respectively. core consumes...
This paper presents a 25-GS/s 4-bit flash analog-to-digital converter (ADC) designed in 28 nm FDSOI CMOS process. A comprehensive analysis of the track-and-hold (T/H) bandwidth requirement is performed, providing design guideline for single-core ADC targeting leading-edge speed performance. 1-to-2 StrongArm latch based demux comparator structure with fat tree thermometer code-to-binary code encoder and body biasing are utilized to reduce power consumption. The achieves SNDR 19.48 dB near...
A power-efficient 2.4 GS/s 10-bit time-interleaved SAR ADC is presented. To reduce the power consumption, several conversion cycles are skipped as input signal falls within a predefined bypass window. enhance operation speed, two alternate comparators adopted in each channel. The comparator offset calibrated only when bit triggered. This eliminates need of dedicated calibration cycle and rate degradation avoided. reference voltage channel provided by pre-charged reservoir to avoid...
This paper presents a 12-bit 60-MS/s SHA-less opamp-sharing pipeline analog-to-digital converter (ADC) implemented in 0.13-μ m CMOS technology. A switch-embedded dual-input current-reused operational transconductance amplifier (OTA) with an overlapping two-phase clocking scheme is proposed to achieve low power consumption and eliminate the non-resetting memory effects observed conventional techniques. To further reduce consumption, ADC also incorporates multi-bit structure. The achieves...
This paper presents an integer-N quotient frequency synthesizer (QFS) for V, E, and W multiband millimeter-wave transceiver applications. Design considerations of passive active components to improve tuning range phase noise LC-VCO are presented. A complementary dual-injection injection-locked divider (ILFD) structure with independent gate biasing is proposed injection efficiency locking range. pseudo-differential cascode buffer developed the stability VCO buffer. The QFS fabricated in a...
This paper presents a quadrature frequency synthesizer (QFS) utilizing switched-coupled slotted inductor (SCSI)-based voltage-controlled oscillator (VCO) to simultaneously improve the reference spurs and out-of-band phase noise while achieving wide tuning range for multiband 5G mm-Wave (mmW) applications. The QFS is implemented in 55 nm CMOS process, of -64 -72 dBc, an in-band -81.7 -87 dBc/Hz at 100 kHz offset -119.1 -125.4 10 MHz offset, respectively, over entire 19.89 26.35 GHz locking...