We present a single-chip array of 100 biologically-based electronic neuron models interconnected to each other and the outside environment through 30,000 synapses. The chip was fabricated in standard 350 nm CMOS IC process. Our approach used dense circuit synaptic behavior, including biological computation learning, as well transistor channel models. use Address-Event Representation (AER) spike communication for inputs outputs this IC. architecture infrastructure, chip, configuration tools,...

Backscatter modulation in radio frequency identification (RFID) tags will potentially connect billions of tomorrow's devices to the Internet-of-Things. Current passive RFID systems have power constraints that limit tag communication short ranges, but these limitations can be overcome by employing reflection amplifiers. In this paper, we show negative differential resistance devices, such as tunnel diodes, exhibit 27 dB more gain and 10 lower consumption than state-of-the-art Two 5.8 GHz...

Statistical analysis of computations per unit energy in processors over the last 30 years is given that illustrates a sharp reduction rate efficiency improvements several resulting formation an asymptotic "wall" with our dataset; we use measure giga multiply accumulates Joule. We have developed model which takes into account realities scaling, specifically for asynchronous systems. Studies efficient pipeline show fabricated results 17 Giga Operations Joule 0.6 μm at subthreshold when fully...

We present a survey and analysis of processor power efficiency, showing results from the first personal computer until day that analyzes metric multiply- accumulate (MAC) energy per operation. MAC performance is critical for continued scaling signal processing applications. derive our published work CPU databases, we hypothesize Powerwall exists, above which do not predict Moore's law will bring current digital computing paradigm. Our show this exists in band 10 to 30 GMAC/W.

Floating-gate (FG) transistors are useful for precisely programming a large array of current sources. Present FG techniques require disconnection the transistor from rest its circuit while it is being programmed. We present new method that does not this disconnection. In indirect method, two share allowing one to exist directly in other reserved programming. Since need be disconnected program it, switch count reduced, resulting fewer parasitics and better overall performance. Additionally,...

Analog circuits and systems research education can benefit from the flexibility provided by large-scale Field Programmable Arrays (FPAAs). This paper presents hardware software infrastructure supporting use of a family floating-gate based FPAAs being developed at Georgia Tech. is compact portable provides user with comprehensive set tools for custom analog circuit design implementation. The includes FPAA IC, discrete ADC, DAC amplifier ICs, 32-Bit ARM microcontroller interfacing user's...

RFID applications have power constraints that limit RF tags to short range communications. This article presents the design procedures, validated by experimental results, make a low-powered reflection amplifier exploits quantum mechanical tunneling effect dramatically enhance of passive or semi-passive tags. A return gain 34.4 dB with bias 45 μW at 5.45 GHz and 22.1 47 5.55 been observed for impinging levels as low -70 dBm. These results allow, certain devices, factor 7 improvement link...

Floating-gate transistors are useful for precisely programming a large array of current sources. Present floating-gate techniques require disconnection the transistor from rest its circuit to be programmed. We present new method indirectly that does not this disconnection. Two share floating gate allowing one exist directly in while other is reserved programming. Since need disconnected program it, switch count reduced, resulting fewer parasitics and better overall performance.

The selection of channel codes for backscatter RFID tag-to-reader communications has always been preoccupied with minimal cost, low chip complexity, power consumption, and the poor sensitivities early-2000s readers. For example, ISO 18000-6C standard UHF tags employs FM0 modulation-an extraordinarily simple scheme that does not maximize throughput. We demonstrate how higher-rate can be applied to link without incurring significant penalties in or read ranges today's a 6/8 balanced block code...

Two novel theorems are developed which prove that certain logic functions more robust to errors than others. These used construct datapath circuits give an increased immunity error over other naive implementations. A link between probabilistic operation and ultra-low energy computing has been shown in prior work. designs will be further improve design of power datapaths. This culminates asynchronous for the maximum amount savings per a given rate. Spice simulation results using commercially...

We present a scheme for using asynchronous trigger modulation in radio frequency integrated circuits (RFICs), which allows more robust backscatter without increasing tag power consumption. Since the implementation does not require load transitions that correspond to regular clock intervals of synchronous logic, whole new class waveforms RFID is also possible, including family perfect pulses provide extra sensitivity long-range tags.

The use of analog floating-gate elements in circuit research has steadily increased. These have great potential because they can be fabricated on a standard process and are low-power. An interesting application for these circuits is the tuning digital threshold power consumption, which been traditionally done by design. We explore floating gates adjustments inverter.

We present an optimized modulation scheme that outperforms EPC UHF Gen2's FM0 protocol in terms of throughput without compromising power consumption, signal fidelity, or RFID chip complexity. analyze a rate 6/8-balance code, which increases by 50%, to show how fidelity and complexity compares favorably the current Gen2 backscatter scheme. This improvement could be used singulate larger fields tags faster retrieve blocks information from sensors/tags future.

This paper investigates the harvesting of RF power using existing electrostatic discharge (ESD) protection circuits most ICs. Because internal diode configuration, a single off-chip capacitor is enough to create charge pump circuit for rectifying and storing sufficient DC passively operate microcontroller. explores ESD circuitry shows feasibility ESD-based harvesting. A proof- of-concept device demonstrates fully-passive backscatter link created MSP430. Backscatter communication achieved...

Motivated by the unwillingness to accept worst-case timing constraint that synchronous logic imposes, and additionally motivated finding a supply voltage scaling scheme for datapath circuits is unconstrained errors in memory elements, authors have built an asynchronous embedded seamlessly into register file. This paper will show not only does arithmetic exhibit many characteristics allow it be inherently lower power, but significantly faster than any counterpart perfect candidate technology...

Analog circuits and systems research education can benefit from the flexibility provided by large-scale Field Programmable Arrays (FPAAs). This demonstration will present visitors with hardware software infrastructure supporting use of a family floating-gate based FPAAs being developed at Georgia Tech. A picture programming control that be demonstrated is found in Figure la. lb shows flow demonstrated. The compact portable provides user comprehensive set tools for custom analog circuit...

The drain current of a transistor in subthreshold operation exhibits temperature dependence due to the thermal voltage, kT/q. magnitude this dependence, as measured 1979, was reported be greater than expected kT/q increased interface state densities; however, thirty years later, we saw little dependence. This behavior is interest because subthreshold-enabled asynchronous circuits allow for below threshold with optimal power performance at threshold, but original work suggests that static...

The Simon Cipher is a low complexity, symmetric cipher that was designed for pervasive computing applications, such as radio-frequency identification (RFID) and Internet of Things; however, there has not been hardware implementation the addresses unique low-power low-device count demands RFID. We present bit-serial guide simontool program, which facilitates design, simulation, verification implementations by emulating an 1-bit in software. This software tool will enable RFID chip designers...

Voltage biases are often required to bias Qubits, and yet applying a static requires separate chip wires, dramatically increasing the system complexity. An ideal approach would be having nonvolatile digital or analog memory avoid these issues. This article shows floating-gate (FG) structures could used set forget potentials tunnel barrier tuning as well enable applications. It reports FG measurements at cryogenic temperatures (T = 4 K), enabling reprogrammable devices in environments. Using...

In this paper, we explore the use of Simon Cipher 4-block key expansion as basis for an unkeyed hash function that is targeted toward RFID and Internet Things applications with benefit reusing existing hardware. A modified used to create a construction can be implemented operate on 2-block cryptographic data from previous round, where number rounds required by are equal cipher.

Floating-gate transistors that have contacts to the lowest metal polysilicon floating-gate were fabricated determine if flow alone could normalize charge across multiple floating gates. The did not for different numbers of polysilicon; however, a decreased variance trapped was found when compared floating-gates no lowestmetal. leakage from negligible after one year, suggesting layout may play critical factor in leakage.

We have designed a subthreshold-enabled FPGA (seFPGA) that has been sent for fabrication. The seFPGA general purpose, but asynchronous architecture contains 50,880 16-bit LUTs with 4 voltage domains. Furthermore, the is appropriate floating-gate or SRAM state storage.

Multiple-Input Translinear Elements (MITEs) are a powerful tool for implementing translinear networks. Large-scale implementations of networks have been plagued by mismatch when implemented in standard CMOS processes. The floating-gate MITE approach allows adjustments to elements post-fabrication compensate process-induced mismatch. In order demonstrate this approach, 2D-vector magnitude circuit and cube root synthesized reprogrammable architecture on 0.35μm, commercially available, process....

A method to approximate nFET passgate resistance using the compact EKV model is presented. The picks a mobility that has greater effect on channel current than higher-order MOS effects in order worst-case over drain-source voltage range. compared data taken from an IC was fabricated 0.5 mum, scalable CMOS process available through MOSIS.