This work describes the use of an anti-phase method to enhance linearity a quad-band CMOS linear power amplifier for EDGE applications. The is applied in process, by studying gm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> characteristic transistor and then operating drive stage subthreshold region cancel nonlinearity stage. fabricated with 0.11 μm RF process packed 44-pin QFN package. It operates GSM-800, EGSM-850, DCS-1800, PCS-1900...

The data retention characteristics of nitride-based charge trap memories using metal–oxide–nitride–oxide–silicon (MONOS) structures employing high-k dielectrics and high-work-function metal gates have been investigated. fabricated MONOS devices with TaN/Al2O3/Si3N4/SiO2/ p-Si show fast program/erase a large memory window greater than 6 V at program erase voltages ±18 V. From bake test high temperatures (200, 225, 250, 275 °C), it is expected to take more 40 years lose less 0.5 loss 85 °C. In...

In this paper, a CMOS antiphase power amplifier (PA) is presented with multigate transistor (MGTR) technique that improves its linearity. The drive stage of the PA biased in subthreshold region, such as class C, to realize technique. nonlinearity canceled out using third-order intermodulation distortion and phase stage. cancellation effect further optimized enhanced without any performance degradation aid proposed MGTR at Unlike traditional technique, which suppresses PA, used enhance cancel...

In this paper, we propose a transceiver architecture for wireless on-wafer test systems. To obtain compact transceiver, the dc-ac converter, an essential component in typical power transfer (WPT) systems, is removed. Instead of output oscillator used as transmitted transmitter. reduce number required inductors and, hence, chip size, inductor cross-coupled transmitter coil. Consequently, proposed becomes sufficiently simple and to be applied verify feasibility topology, designed using 180-nm...

We propose a mode-locking method optimized for the cascode structure of an RF CMOS power amplifier. To maximize advantage typical in structure, input cross-coupled transistor is modified from that structure. prove feasibility proposed we designed 2.4 GHz amplifier with 0.18 μ m RFCMOS process polar transmitter applications. The measured added efficiency 34.9%, while saturated output 23.32 dBm. chip size is<mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML"...

In this review article, a stage-convertible RF power amplifier designed with 0.18-μm CMOS process is described. A method to implement low-power matching network an essential technology for the amplifier. Various networks distributed active transformers as output combiner are compared in terms of amounts undesired coupling, chip size, and amount loss. The feasibility differential line inductor assessed explained. Finally, we show that realistic means reducing overall enhancing quality factor...

A wireless type of chip-to-chip communication (WCC) technology is proposed as the next generation 3D semiconductor technology. To demonstrate feasibility this technology, we designed a coil, transmitter and receiver for using 50-nm digital CMOS process. The coil inductive coupling with design parameters that include number turns, metal width, space between adjacent lines. differential transceiver structure WCC acts termination bias circuit while operating receiver. typical amplifier latch to...

We propose a power detection method for RF CMOS amplifier applications using the second harmonic component at virtual ground node. With proposed method, we remove fundamental signal distortion problems. Because input of detector is node amplifier, ripple voltage can be reduced compared to when used. designed simple with and verify feasibility method.

ABSTRACT In this work, we design a linear CMOS power amplifier with spiral‐type output transformer for IEEE 802.11n WLAN applications. We conduct studies to identify the proper and stage structures amplifiers. The is composed of single differential‐pair mitigate stability problems that frequently arise in high gain Additionally, investigate matching network using minimize return loss. To verify feasibility amplifier, designed 2.4‐GHz 180‐nm SOI process. measured an signal. achieves 21.28 dBm...

In this study, we design a differential power amplifier using 110-nm RF CMOS process. To improve gain, propose an active balun as driver stage of the amplifier. The passive input is removed to minimize substrate loss. proposed structure, converts single-ended signal into and at same time provides sufficient gain stage. verify feasibility designed typical identical processes with parameters, except for transformer measured improvement approximately 4.2 dB compared that From results, successfully prove

ABSTRACT In this work, we analyzed numerically the effects of an interstage capacitor related to power‐added efficiency a power amplifier. particular, calculated consumption values induced by on‐resistances and short‐circuit current class‐D‐type driver‐stage. After analyzing results, between driver stages was removed improve overall efficiency. By removing capacitor, supply voltage for stage can be decreased compared normal The at on‐resistance reduced reduced. Additionally, measured verify...

In this work, we propose a 24-GHz VCO using transformer. the mm-wave band, parasitic components of passive device and feeding line degrade performance. To reduce undesired effects devices, replaced transformer instead devices such as inductor or capacitor. addition, frequency tuning technique gate bias typical varactor. verify feasibility proposed structure, designed 110-nm RFCMOS process. The measured range was 22.7 to 24.2 GHz, it had output power 8.4 dBm at 24 GHz. phase noise -95.33...

In this study, we propose an auxiliary power regulator (APR) for the current-shared cascade (CSC) structure of driver stages RF CMOS power. Although CSC provides a method to reduce consumption at differential amplifier (PA), it is difficult obtain optimum levels effective supply voltage first and second stages. Additionally, transistor sizes must be identical ensure proper operation PA. Thus, in work, APR that ensures PA with different its To prove feasibility proposed technique, designed...

We present the possibility of a complementary metal-oxide semiconductor (CMOS) power amplifier (PA) using driver stage composed p-channel metal oxide (PMOS) to enhance linearity. The PMOS is designed as cascode structure adapt antiphase technique CMOS PA. By biasing common-source transistor at subthreshold region, we obtain gm3 value with positive sign cancel out negative stage, thereby enhancing also investigate effect bias on third-order intermodulation distortion and amplitude-to-phase...

Abstract In this work, we propose a differentially coupled series inductor for RFIC‐matching networks. The proposed is designed to reduce the chip area and enhance inductance. If required in differential RFICs, two bulky inductors should be implemented. overall size thereby increases considerably. can used instead of RFIC. less than half that conventional spiral inductors. From measured results, feasibility successfully proved. © 2015 Wiley Periodicals, Inc. Microwave Opt Technol Lett 57:2223–2225,

ABSTRACT This article describes a highly efficient X‐band CMOS power amplifier. To obtain high drain voltage for power, instead of using the typical cascode structure, we use common‐source structure with long channel length transistor. Generally, to enable operating speed at frequency, smaller transistor technology is used, but demonstrate that large also possible. The proposed amplifier designed transistors 300‐nm in differential RFCMOS technology. Consequently, maximum output 19 dBm added...

This paper represents a CMOS RF power amplifier using current combining technique to improve the linearity of WLAN applications. technique, based on transformer, is composed partially combined 2-metal layers minimize resistive loss induced by transformer. To verify feasibility proposed 180-nm process, we obtain measured output 19 dBm with EVM -25 dB in 802.11b/g modulated.

In this paper, we propose a zigzag-shaped coil array structure for wireless chip-to-chip communication. The proposed is designed high-speed memory, which requires pad number on the order of tens. First, general investigated with respect to undesired coupling between adjacent coils. We also shielding patterns are inserted coils reduce cross-talk problems. To solve and chip area problems associated arrays, zigzag pattern proposed. Additionally, layout technique circuit block memory transceiver...

ABSTRACT In this work, we propose a gain and stability enhancement technique with compact size for RF CMOS linear power amplifier applications. The proposed is designed differential cascode structures. To realize of the amplifier, driver stage merged into amplifier. minimize number essentially required inductors, load impedance shared Additionally, to moderate problems in closed loop removed using common‐gate transistor, which operates saturation region. can then operate operation. prove...

In this work, we report improved endurance of p-type floating-gate NAND flash cell. The physical model on the and data retention cells is proposed verified by using device simulation to elucidate cause that floating gate has better than n-type floating-gate. hole currents injected from Si substrate begin participate in erase operation contribution holes results more probable hole-trapping neutralizing electron trap a tunnel oxide with cycling stress. Such compensation effect thought induce cell

In this work, we propose a merged coil structure for wireless chip-to-chip communication technology. Using the proposed structure, chip size can be reduced, and transmitted power improved by approximately 5dB compared to typical structure. To verify feasibility of coil, an electromagnetic simulation schematic are performed. The was implemented using 50-nm digital CMOS From experimental results, proved.