Lingjuan Wu

ORCID: 0000-0002-7624-2706
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About
Contact & Profiles
Research Areas
  • Physical Unclonable Functions (PUFs) and Hardware Security
  • Advanced Malware Detection Techniques
  • Integrated Circuits and Semiconductor Failure Analysis
  • Adversarial Robustness in Machine Learning
  • Security and Verification in Computing
  • Error Correcting Code Techniques
  • Interconnection Networks and Systems
  • Parallel Computing and Optimization Techniques
  • Neuroscience and Neural Engineering
  • Cryptographic Implementations and Security
  • Wireless Communication Security Techniques
  • Digital Image Processing Techniques
  • Explainable Artificial Intelligence (XAI)
  • Cooperative Communication and Network Coding
  • Radiation Effects in Electronics
  • Access Control and Trust
  • Cloud Data Security Solutions
  • Machine Learning and Algorithms
  • Machine Learning and Data Classification
  • Tropical and Extratropical Cyclones Research
  • Anomaly Detection Techniques and Applications
  • Graph Theory and Algorithms
  • Statistical Methods and Inference
  • VLSI and Analog Circuit Testing
  • Computer Graphics and Visualization Techniques

Huazhong Agricultural University
2019-2025

Northwestern Polytechnical University
2020-2021

Xi'an Jiaotong University
2019

Trojans represent a severe threat to hardware security and trust. This work investigates the Trojan detection problem from unique viewpoint proposes novel localization method targeting FPGA netlists. The proposed automatically extracts rich structural behavioral features at look-up-table (LUT) level train an explainable graph neural network (GNN) model for classifying design nodes in netlists identifying Trojan-infected ones. Experimental results using 183 benchmarks show that our...

10.1109/tcad.2025.3527377 article EN IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 2025-01-01

This work proposes a novel hardware Trojan detection method that leverages static structural features and behavioral characteristics in field programmable gate array (FPGA) netlists. Mapping of design sources to look-up-table (LUT) networks makes these explicit, allowing automated feature extraction further effective through machine learning. Four-dimensional are extracted for each signal random forest classifier is trained net classification. Experiments using Trust-Hub benchmarks show...

10.1109/host54066.2022.9840276 article EN 2022-06-27

Taint-propagation and X-propagation analyses are important tools for enforcing circuit design properties such as security reliability. Fundamental to these effective models accurately measuring the propagation of information calculating metadata. In this work, we formalize a unified model reasoning about taint- behaviors verifying related behaviors. Our developed from perspective flow can be described using standard hardware description language (HDL), which allows formal verification both...

10.1109/ats49688.2020.9301533 article EN 2020-11-23

Masking is a commonly used countermeasure for protecting cryptographic implementations from power side channel analysis. Rotating S-Box masking (RSM) state-of-the-art technique, whose effectiveness has been testified in ongoing worldwide DPA contest. However, does not provide sufficient protection against active attacks through fault injection. In this paper, we propose simple yet effective correlation attack on two generations of RSM AES schemes. We demonstrate mathematical formulations...

10.1109/asianhost53231.2021.9699812 article EN 2021-12-16

10.1109/globecom52923.2024.10901102 article EN GLOBECOM 2022 - 2022 IEEE Global Communications Conference 2024-12-08

Neural networks have been successfully applied in numerous domains with the help of high-quality training samples. However, datasets containing noises and outliers (i.e., corrupted samples) are ubiquitous real world. When using these as samples, most neural exhibit poor predictive performance. In this paper, motivated by modal regression, we propose a Modal Network, which is robust to Specifically, network can reveal likely trends samples without overfitting On theoretical side, establish...

10.1109/ijcnn54540.2023.10191062 article EN 2022 International Joint Conference on Neural Networks (IJCNN) 2023-06-18

Recently, adversarial metric learning has been proposed to enhance the robustness of learned distance against perturbations. Despite rapid progress in validating its effectiveness empirically, theoretical guarantees on and generalization are far less understood. To fill this gap, paper focuses unveiling properties by developing uniform convergence analysis techniques. Based capacity estimation covering numbers, we establish first high-probability bounds with order O(n^{-1/2}) for pairwise...

10.24963/ijcai.2023/489 article EN 2023-08-01

Abstract Large-scale Agent data partitioning is the premise of parallel distributed computing in process ABMS (Agent-based Modeling and Simulation) . Based on distance-based K_medoids clustering algorithm, this paper proposes an improved algorithm (DensityRepel-K_medoids), which implemented by high-performance programming language X10 applied to large-scale simulation based distance interaction. The DensityRepel-Kmedoids first determines density value repulsion each set, secondly pre-selects...

10.1088/1742-6596/1284/1/012046 article EN Journal of Physics Conference Series 2019-08-01

Consortium blockchain has been widely used in different scenarios, where members demand that their uploaded data could be audited under identities without exposing the themselves. However, so far, no solution of privacy-preserving auditing proposed. To address problem, we propose zkrpChain, which focuses on protection integrity and privacy by while leaving public. In is based Hyperledger Fabric Bulletproofs, both standard-range arbitrary-range zero-knowledge range proofs generation...

10.1109/trustcom50675.2020.00092 article EN 2021 IEEE 20th International Conference on Trust, Security and Privacy in Computing and Communications (TrustCom) 2020-12-01

Symmetric cryptographic functions are known to leak secret information through power side channels. Although masking provides an effective mitigation such leakage, these protection designs vulnerable advanced side-channel analysis based on machine learning. In this work, we propose a framework leverage ensemble learning for masked AES implementation. Before the key recovery, use techniques including decision tree, random forest, BP nerual network, and recover masks. We also implement data...

10.1109/iccc54389.2021.9674477 article EN 2021 7th International Conference on Computer and Communications (ICCC) 2021-12-10

Graphics Processing Unit (GPU) performs graphics computing and its architecture has developed from the fixed function pipeline to programmable unified pipeline. Unified promises dynamic load balancing guarantees high parallel of GPU. This paper presents design implementation a The shader is based on SIMD SIMT architecture. On thread level, full-load capability by managing scheduling. instruction controls execution hardware unit. We finish algorithm, Verilog RTL implementation. verification...

10.22323/1.299.0079 article EN cc-by-nc-nd 2017-07-17

Satisfiability don't cares (SDCs) have recently been exploited for malicious design modifications, where an SDC signal pair is used as two discrete Trojan triggers. The care condition can never be satisfied under normal operation and the only activated through fault injection. However, each trigger able to switch normally. Consequently, Trojans are resilient state-of-the-art side channel well switching probability analysis based detection techniques. In this paper, we propose a novel method...

10.1109/socc52499.2021.9739555 article EN 2021-09-14

Software attacks that exploit the hardware security vulnerabilities of processors have become new breakthrough points for hackers, which pose severe threats to and trust. This paper proposes a novel system verification method based on instruction set architecture (ISA) level information flow tracking (IFT), is capable modeling checking properties in both software designs. We use RISC-V as demonstration, lately developed open-source ISA widely used Internet Things facing due universal...

10.1109/ats59501.2023.10317944 article EN 2023-10-14

Third-party intellectual property cores are essential building blocks of modern system-on-chip and integrated circuit designs. However, these design components usually come from vendors different trust levels may contain undocumented functionality. Distinguishing such stealthy lightweight malicious modification can be a challenging task due to the lack golden reference. In this work, we make step towards for assurance by developing method identifying preventing hardware Trojans, employing...

10.48550/arxiv.2311.12321 preprint EN other-oa arXiv (Cornell University) 2023-01-01

Trojan horses represent a major threat to hardware security and trust. In this work, we propose novel detection method based on explainable graph neural networks (GNNs) targeting FPGA netlists. We leverage the rich explicit structural features behavioral characteristics at LUT, which offers an ideal abstraction level granularity for detection. A GNN model with optimized class-balanced focal loss is trained automated feature extraction classification. Based Granger causality theory, develop...

10.1109/iccad57390.2023.10323915 article EN 2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) 2023-10-28

10.1007/s11704-023-2662-3 article EN Frontiers of Computer Science 2023-12-28

In this letter, we consider the proof of non-stationary channel polarization theory. First construct a multi-channel stochastic process for operation. Then based on process, extend Ar{\i}kan's standard martingale method average capacity and Bhattacharyya parameter, by which have proved

10.48550/arxiv.1812.00160 preprint EN other-oa arXiv (Cornell University) 2018-01-01

High performance 3D graphics processor is one of the most important hardware modules in modern mobile SoC design. This paper presents design a fully programmable taking advantage unified shader architecture for applications. We adopt multi-thread scheduling to utilize data, instruction parallelism and reduce data dependency stalls. In core design, we single multiple (SIMD) support four concurrent scalar operation. Moreover, propose novel special function unit floating point transcendental...

10.1109/asicon47005.2019.8983613 article EN 2021 IEEE 14th International Conference on ASIC (ASICON) 2019-10-01
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