Heterogeneous embedded systems on chip (HESoCs) co-integrate a standard host processor with programmable manycore accelerators (PMCAs) to combine general-purpose computing domain-specific, efficient processing capabilities. While leading companies successfully advance their HESoC products, research lags behind due the challenges of building prototyping platform that unites an industry-standard open PMCA architecture. In this work we introduce HERO, FPGA-based combines composed clusters...

Heterogeneous systems on chip (HeSoCs) co-integrate a high-performance multicore host processor with programmable manycore accelerators (PMCAs) to combine "standard platform" software support (e.g. the Linux OS) energy-efficient, domain-specific, highly parallel processing capabilities.

With the shrinking of technology nodes and use parallel processor clusters in hostile critical environments, such as space, run-time faults caused by radiation are a serious cross-cutting concern, also impacting architectural design. This paper introduces an approach to configurable soft-error tolerance at core level, augmenting six-core open-source RISC-V cluster with novel On-Demand Redundancy Grouping (ODRG) scheme. ODRG allows operate either two fault-tolerant cores, or six individual...

A key enabler for the ever-increasing adoption of FPGA accelerators is availability frameworks allowing seamless coupling to general-purpose host processors. Embedded FPGA+CPU systems still heavily rely on copy-based host-to-accelerator communication, which complicates application development. In this paper, we present a hardware/software framework enabling transparent, shared virtual memory in embedded SoCs. It can use hard-macro IOMMU if available, or configurable soft-core that provide....

One of the most demanding tasks in state-of-the-art medical ultrasound systems is localization possible scatterers body based on received echoes. Digital beamforming involves summation all echoes each image point according to their time flight, i.e., delay. This requires knowledge delays for combinations transmitters, points and receivers. Recent three-dimensional (3D) comprise thousands transducer elements millions points. Compared traditional 2D systems, total number several orders...

While high-end heterogeneous systems are increasingly supporting uniform memory access (hUMA), their low-power counterparts still lack basic features like virtual support for accelerators. Instead of simply passing pointers, explicit data management involving copies is needed which hampers programmability and performance. In this work, we evaluate a mixed hardware/software solution lightweight many-core accelerators in embedded systems-on-chip. Based on an input/output translation lookaside...

Shared virtual memory is key in heterogeneous systems on chip (SoCs) that combine a general-purpose host processor with many-core accelerator, both for programmability and performance. In contrast to the full-blown, hardware-only solutions predominant modern high-end systems, lightweight hardware-software co-designs are better suited context of more power- area-constrained embedded provide additional benefits terms flexibility predictability. As downside, latter require handle software...

Fault attacks are active, physical that an adversary can leverage to alter the control-flow of embedded devices gain access sensitive information or bypass protection mechanisms. Due severity these attacks, manufacturers deploy hardware-based fault defenses into security-critical systems, such as secure elements. The development countermeasures is a challenging task due complex interplay circuit components and because contemporary design automation tools tend optimize inserted structures...

Shared virtual memory (SVM) is key in heterogeneous systems on chip (SoCs), which combine a general-purpose host processor with many-core accelerator, both for programmability and to avoid data duplication. However, SVM can bring significant run time overhead when translation lookaside buffer (TLB) entries are missing. Moreover, allowing DMA burst transfers write traditionally requires buffers absorb that miss the TLB. These have be overprovisioned maximum size, wasting precious on-chip...

While high-end heterogeneous systems are increasingly supporting uniform memory access (hUMA) as envisioned by the Heterogeneous System Architecture (HSA) foundation, their low-power counterparts targeting embedded domain still lack basic features like virtual support for accelerators. As opposed to simply passing address pointers, explicit data management involving copies is needed share between host processor and accelerators which hampers programmability performance. In this work, we...

High-frame-rate and high-resolution 3D medical ultrasound imaging imposes high requirements on the involved processing hardware. Several thousands of analog signals need to be processed in many steps obtain a final image. Fully digital beamforming makes it possible achieve image quality coupled with extreme flexibility. Unfortunately, staggering main memory bandwidth caused by loading off-chip stored delays. In this paper we present first fully-digital integrated beamformer that is able...

Heterogeneous embedded systems on chip (HESoCs) co-integrate a standard host processor with programmable manycore accelerators (PMCAs) to combine general-purpose computing domain-specific, efficient processing capabilities. While leading companies successfully advance their HESoC products, research lags behind due the challenges of building prototyping platform that unites an industry-standard open PMCA architecture. In this work we introduce HERO, FPGA-based combines composed clusters...

Today's systems-on-chip (SoCs) more and conform to the models envisioned by Heterogeneous System Architecture (HSA) foundation in which massively parallel, programmable many-core accelerators (PMCAs) not only cooperate but also coherently share memory with a powerful, multi-core host processor. Allowing direct access system from both sides greatly simplifies application development, it increases potential interference due PMCA.

While high-end heterogeneous systems are increasingly supporting uniform memory access (hUMA) as envisioned by the Heterogeneous System Architecture (HSA) foundation, their low-power counterparts targeting embedded domain still lack basic features like virtual support for accelerators. As opposed to simply passing address pointers, explicit data management involving copies is needed share between host processor and accelerators which hampers programmability performance. In this work, we...

This paper presents an approach for investigating the statistical behavior of voltage harmonic distortions on a commercial load. Stochastic process tools are proposed analyzing problem total distortion (THD). Voltage signals used to perform study. Indices such as probability and time means employed verifying condition stationarity whether both processes present similarity. Field measurements obtained from load assess test results. The analysis permits establish typical period, which better...

A CMOS VLSI system on chip, designed for irrigation control applications was developed. The SoC features include wireless communication capability, data processing, sensor signal acquisition and actuator control. power saving strategy provides long-term autonomy with standard energy sources. Application software dedicated development CAD tools were also implemented in this design effort.

Carrier aggregation (CA) in latest 4G standards and beyond demands either multiple narrow-band RX branches or a single wide-band branch followed by efficient channelizer architectures the digital front-end (DFE). The small number of simultaneously received component carriers favors use ADC conjunction with per-channel carrier extraction. However, computational complexity extraction is high due to mixing operation for each aggregated carriers. In this work, we show how approach can be reduced...

Shared virtual memory (SVM) is key in heterogeneous systems on chip (SoCs), which combine a general-purpose host processor with many-core accelerator, both for programmability and to avoid data duplication. However, SVM can bring significant run time overhead when translation lookaside buffer (TLB) entries are missing. Moreover, allowing DMA burst transfers write traditionally requires buffers absorb that miss the TLB. These have be overprovisioned maximum size, wasting precious on-chip...

With the shrinking of technology nodes and use parallel processor clusters in hostile critical environments, such as space, run-time faults caused by radiation are a serious cross-cutting concern, also impacting architectural design. This paper introduces an approach to configurable soft-error tolerance at core level, augmenting six-core open-source RISC-V cluster with novel On-Demand Redundancy Grouping (ODRG) scheme. ODRG allows operate either two fault-tolerant cores, or six individual...

Fault attacks are active, physical that an adversary can leverage to alter the control-flow of embedded devices gain access sensitive information or bypass protection mechanisms. Due severity these attacks, manufacturers deploy hardware-based fault defenses into security-critical systems, such as secure elements. The development countermeasures is a challenging task due complex interplay circuit components and because contemporary design automation tools tend optimize inserted structures...