Recently, the demand for portable electronics and embedded systems has increased. These devices need low-power circuit designs because they depend on batteries as an energy resource. Moreover, multi-valued logic (MVL) circuits provide notable improvements over binary in terms of interconnect complexity, chip area, propagation delay, consumption. Therefore, this paper proposes new ternary aiming to lower power delay product (PDP) save battery The proposed include gates [standard inverter...

The embedded systems, IoT (Internet of Things) devices, and portable electronic devices spread very quickly recently. Most them depend on batteries to operate. target this work is decrease energy consumption by (1) using Multiple-valued logic (MVL) that shows notable enhancements regarding over binary circuits (2) carbon nanotube field-effect transistors (CNFET) show better performance than CMOS. This proposes ternary combinational 32 nm CNFET: Ternary Half Adder (THA) with 36 Multiplier...

Multi-valued logic (MVL) has more than two-valued to decrease the interconnections and energy consumption. Also, market seen a significant increase in portable electronics embedded systems, which depend on batteries. Therefore, this paper proposes 32 nm channel CNFET-Based Ternary Half Adder (THA) "decoder-less" Multiplexer (TMUX) using proposed Unary Operator aiming power-delay product (PDP) preserve battery consumption; Simulations performed HSPICE simulator for voltage variation,...

Multiple-Valued Logic systems present significant improvements in terms of energy consumption over binary logic systems.This paper proposes new ternary combinational digital circuits that reduce low-power nano-scale embedded and Internet Thing (IoT) devices to save their battery consumption.The 32 nm CNTFET-based half adder (THA) multiplier (TMUL) use novel unary operator implement two power supplies Vdd Vdd/2 without using any decoders, basic gates, or encoders minimize the number used...

The design of the Ternary Full Adders (TFA) employing Carbon Nanotube Field-Effect Transistors (CNFET) has been widely presented in literature. To obtain optimal these ternary adders, we propose two new different designs, TFA1 with 59 CNFETs and TFA2 55 CNFETs, that use unary operator gates voltage supplies (Vdd Vdd/2) to reduce transistor count energy consumption. In addition, this paper proposes 4-trit Ripple Carry (RCA) based on proposed TFA2; HSPICE simulator 32 nm CNFET simulate...

Energy consumption is a critical factor to be reduced when designing embedded systems and IoT devices. By using Multiple-valued logic (MVL) circuits, interconnections complexity energy are decreased in comparison binary systems. This paper uses MVL circuits present ternary half-adder (THA) with maintain the battery usage nano-scale The proposed CNTFET-based circuit dualvoltage (Vdd Vdd/2) novel unary operators improve performance. Extensive HSPICE simulations show impressive improvements...

Multiple-valued logic (MVL) circuit has many-valued in each digit to lower interconnections and energy consumption over a binary circuit. Therefore, this paper proposes ternary multiplier (TMUL) that reduce the context of low-power embedded circuits. The CNTFET-based TMUL use only cascading proposed multiplexer transistors count improve performance efficiency. Extensive simulations along with several benchmark designs using HSPICE, prove merits by reducing consumption, improving noise...

This paper proposes a novel implementation of Ternary Decoder using CMOS DPL (Double Pass Logic) Binary logic gates, in digital technology. The physical design the circuits is simulated and tested with Micro-Cap 10 SPICE simulator. Proposed circuit can be used VLSI design. decoder will basic to create other Logic Circuits like Gates, Memory, Adder, Multiplier, Multiplexer, others. simulation results demonstrate merits approach terms reduced number transistors by 25% compared existing ternary decoder.

The ternary circuit has an advantage over the binary concerning interconnect complexity, propagation delay, and energy consumption. This paper proposes a novel binary-to-ternary converter using Double Pass-Transistor (DPL) with four bits as input three trits output. importance of this work is gained through its potential to increase data rate, reduce power Also, proposed can be used bridge between circuits. simulated tested Micro-Cap V10 PSPICE simulator CMOS process technology. It then...

This work proposes models for a L-trit TMUL (Ternary Multiplier) and THA (Half-Adder) using TMUXs Multiplexers) unary operators. The target of the proposed designs is to minimize energy consumption in nanoscale embedded circuits improve their battery usage. To achieve that, different techniques are used: 32-nm CNTFET tranisistor, Multiple-Valued Logic (MVL), two voltage supplies <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(V_{dd},\...

Software-Defined Networking (SDN) revolutionizes network management by decoupling control plane functionality from data devices, enabling the centralized and programmability of behavior. This paper uses ternary system to improve Central Processing Unit (CPU) inside SDN controller enhance management. The Multiple-Valued Logic (MVL) circuit shows remarkable improvement compared binary regarding chip area, propagation delay, energy consumption. Moreover, Carbon Nanotube Field-Effect Transistor...

The study presents a new approach for assessing plantarflexor muscles' function using smartphone. test involves performing repeated heel raises 60 s while seated. seated heel-rise offers simple method in those with severe balance impairment who are unable to complete tests performed standing. aimed showcase how gyroscopic data from smartphone placed on the lower limb can be used assess test. Eight participants each limb. Gyroscope and 2D video analysis (60 Hz) of motion were determine number...

The limitations in binary data transmission are mainly for low speed and a notable increase energy consumption. Whereas, Multiple-Valued Logic (MVL) has over two-valued logic to the reduce Therefore, this paper proposes Ternary-to-Binary Converter based on Carbon Nano-Tube Field Effect Transistors (CNFETs) be used ternary transmission. proposed converter two trits as input four bits output. Logical analysis simulation results, using HSPICE simulator, prove merits of implementation compared...

In information theory, the Hamming distance between two strings of equal length is number positions at which corresponding symbols are different. It measures minimum substitutions required to change one string into other, or errors that transformed other. The process detecting in a sequence bits determined by comparing this dictionary encodings, if found then pattern correct, otherwise an error has occurred. order correct errors, original substituted with closest dictionary, i.e. smallest...

Since smart phones are equipped with built-in accelerometers they can be used for self-monitoring of physical activity which is an important health behavior and predictor functioning, especially in older adults. The objective this study to investigate the validity a phone-based monitoring application adults aged below above 65 years old. Ten (mean 33, standard deviation 13.7) ten or 76, 5.5) were asked monitor their daily phone ActiGraph GT3X 7 consecutive days. Spearman correlations between...

This thesis proposes novel ternary circuits aiming to reduce energy preserve battery consumption. The proposed designs include eight logic gates, three combinational circuits, and six Ternary Arithmetic Logic Units. applies the best tradeoff between reducing number of used transistors, utilizing efficient transistor arrangements such as transmission applying dual supply voltages achieve its objective. are compared latest using HSPICE simulator for different voltages, temperatures,...

The reduction trees of combinational multipliers are widely applying counters. To be able to compare the ternary and binary approaches, Nanotube Field-Effect Transistor (CNTFET) (3,2) (4,2) counters have been designed. counter is compared with (7,3) as both compute approximately same amount information. more efficient. However, comparing not enough: in Wallace tree multiplier, there two times lines reduce one, a 1-trit multiplier generates product carry terms. Comparing an 8*8-trit 12*12-bit...

This paper compares the performance of ternary adders and multipliers using balanced unbalanced set values. We use 1-trit to evaluate two versions a 4-trit propagate adder, which are comparedwith 6-bit corresponding adder. Similarly, we compare types 2*2 trit with a3*3 bit multiplier. The simulations 32-nm Carbon Nanotuble Field-Effect Transistor (CNTFET) technology show that binary more efficient than ones compute same amount information

The accelerometers implanted into smart phones can be used as a self monitoring device for daily physical activity in elderly population. study goal is to validate the phone-based application adults aged below and above 65 years old. Ten young (mean of 33, SD 13.7) ten 76, 5.5) were asked monitor their with phone an ActiGraph GT3X 7 consecutive days. Each minute both devices was classified one four different levels: sedentary, light, moderate high. Minutes count from each level between...