Current research on code clones tries to address the question whether or not are harmful for quality of software. As most these studies based fine-grained analysis inconsistent changes at revision level, they capture much chaotic and experimental nature inherent any ongoing software development process. Conclusions drawn from inspection highly fluctuating short-lived likely exaggerate ill effects changes. To gain a broader perspective, we perform an empirical study effect release level....

This paper studies the reliability of three different majority gates full adder (FA) designs, and compares them with that a standard XOR-based FA. The analysis provides insights into parameters affect FAs. probability transfer matrix method is used to exactly calculate FAs under investigation. All simulation results show are more robust than They also how FAs' reliabilities extrapolated give estimates from device level. Such analyses should be for better characterization FA designs future...

Scaling complementary metal oxide semiconductor (CMOS) devices has been a method used very successfully over the last four decades to improve performance and functionality of large scale integrated (VLSI) designs. Still, scaling is heading towards several fundamental limits as feature size being decreased 10 nm less. One challenges associated with expected increase static dynamic parameter fluctuations variations, well intrinsic extrinsic noises, significant effects on reliability....

Generic as well customized reliability electronic design automation (EDA) tools have been proposed in the literature and used to estimate of both present future (nano)circuits. However, accuracy many these EDA is questionable they: 1) either assume that all gates same constant probability failure ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">PF</i> <sub xmlns:xlink="http://www.w3.org/1999/xlink">GATE</sub> =...

Power dissipation and reliability are two major challenges when designing gates circuits using nanoscale devices. This paper proposes a novel approach for the design of CMOS logic which aims to simultaneously decrease their power consumption probabilities failure. new sizing method was evaluated on inverters NOR-2 at three technology nodes: 16nm, 22nm, 32nm. The were compared classic gates. results show that have significantly lower higher also suggest advantages enhanced smaller feature...

This paper starts by reviewing many of the gate-level reliability analyses von Neumann multiplexing (vN-MUX). It goes on to detail very accurate device-level (CMOS technology specific) vN-MUX with respect threshold voltage variations, taking into account both gates' topology as well input vectors. Such results are essential for a clear understanding when considering unreliable behavior future nanodevices. These should change "view from top" revealing different picture well-known theoretical...

Introducing redundancy at the device-level has been proposed as most effective way to improve reliability. With remarkable reliability of complementary metal oxide semiconductor (CMOS) transistors industry was able fabricate, research on reduced. However, increasing sensitivity noise and variations (due massive scaling) CMOS led a revival interest in schemes during last decade. In this paper, we introduce novel transistor sizing method that can be used significantly reduce probability...

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As the sizes of CMOS devices rapidly scale deep into nanometer range, manufacture nanocircuits will become extremely complex and inevitably introduce more defects, including transient faults that appear during operation. For this reason, accurately calculating reliability future designs be critical for nanocircuit designers as they investigate design alternatives to optimize tradeoffs between area-power-delay reliability. However, accurate calculation large highly connected circuits is very...

This paper will briefly review nanoelectronic challenges while focusing on reliability. We shall present and analyze a series of CMOS-based examples for addition starting from the device level moving up to gate, circuit, block level. Our analysis, backed by simulation results, comparing parallel serial shows that adders are more reliable also dissipating less. Their reliability can be improved using reliability-enhanced gates and/or other redundancy techniques (like e.g., multiplexing)....

The high-level approach for estimating circuit reliability tends to consider the probability of failure a logic gate as constant, and work towards higher levels. With scaling, such gate-centric approaches become highly inaccurate, both transistors input vectors drastically affect gates. This paper will present transistor-level analysis starting from threshold voltage variations. We briefly review state-of-the-art, rely upon freshly reported results These be used estimate probabilities...

This paper suggests a transistor sizing method for classical CMOS gates implemented in advanced technology nodes and operating at low voltages. The relies on upsizing the length (L) of all transistors uniformly, balancing voltage transfer curves (VTCs) maximizing static noise margins (SNMs). We use most well-known (INV, NAND-2, NOR-2) introducing novel method, as well validating concept evaluating its performances. results show that has not entirely exhausted potential, allowing to go beyond...

In this paper we present the first detailed analysis of von Neumann multiplexing (vN-MUX) using majority (MAJ) gates small fan-ins Δ (MAJ-Δ) with respect to probability failure elementary (nano-)devices. Only have been considered, as large do not seem practical (at least in short term) future technologies. The extensions from an exact counting algorithm (for gate defects and faults only) device-level failures will allow us estimate characterize MAJ-Δ vN-MUX malfunctions. reported results...

Peer-to-peer (P2P) systems are constructed to provide resource sharing among interested participants (peers) in a dis- tributed and self-organized fashion. The way P2P networks formed is critical the overall system performance due communications network maintenance overhead. Mobile environments pose additional challenges on heterogeneity of nodes, inherent limited resources, dynamic context wireless characteris- tics. This paper presents RobP2P, robust architecture construct mobile...

Denial of Service (DoS) attacks are important topics for security courses that teach ethical hacking techniques and intrusion detection. This paper presents a case study the implementation comprehensive offensive hands-on lab exercises about three common DoS attacks. The students how to perform practically in an isolated network laboratory environment. discuses also some legal issues related teaching hacking, then lists steps schools educators should take improve chances having successful...

Scaling the CMOS devices deep into nanorange reduces their reliability margins significantly. Consequently, accurately calculating of digital nanocircuits is becoming a necessity for investigating design alternatives to optimize trade-offs between area-power-delay and reliability. However, accurate calculation large highly connected circuits complex very time consuming. This paper proposes progressive consensus-based algorithm identifying worst input vectors associated critical logic gates....

Until recently, reliability was not considered to be a major design concern for circuit designers, except in the case of space and mission critical applications. However, aggressive scaling CMOS devices has significantly affected their reliable operation. Several schemes have been used mitigating effects maintaining above certain threshold. Many these rely on incorporating different types redundancy at device, gate, system level, which inevitably affect area, power, delay parameters. To...

This paper investigates the behavior of multiplexing (MUX) schemes in combination with elementary gates. The two under investigation are majority (MAJ) and NAND MUX. simulation results presented here for single-electron technology, but could easily be extended to CMOS. components gates have been subjected only geometric variations. Firstly, MUX analyzed theoretically. Secondly, simulations using probability transfer matrices (PTM) allow evaluating both at a redundancy factor R = 6. Finally,...

Reducing the supply voltage is by far most widely used low-power technique, as reducing dynamic power quadratically and leakage linearly, while sacrificing on performances. A similar but less explored route to reduce and/or limit currents (instead of voltages), e.g., through transistor sizing. This paper details a comparison reverse-sized CMOS scheme (which reduces currents), with both classical implementation an ultra low (ULP) sub-threshold scheme. Simulation results show that inverter...

Full adders (FAs) are essential for digital circuits including microprocessors, signal processors, and microcontrollers. Both the power consumption reliability of FAs crucial as they directly affect: arithmetic logic units, floating-point well memory address calculations. This paper studies effect threshold voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</sub> ) variations play on a classical 28-transistor FA, shows that can be...