In this brief, we introduce a priority encoder that uses novel lookahead (PL) scheme to reduce delays associated with propagation. Two approaches are presented, one without and the other PL scheme. For an N-bit encoder, circuit requires about 0.1 more transistors than However, 32-bit very large scale integration (VLSI) is 2.5 times faster encoder. The worst case operation delay 4.4 ns for using 1 /spl mu/m scalable complementary metal-oxide-semiconductor (CMOS) technology.

This paper discusses the many challenges in design of future nano architectures that result from use nanoelectronic devices. The relations among these are studied, and an unfortunately subjective relative ranking is proposed. Possible solutions suggested.

In this paper, a novel hybrid wave pipelined bit-pattern associative router (BPAR) is presented. A an important component in communication network systems. The BPAR allows for flexibility and can accommodate large number of routing algorithms. study, approach has been proposed implemented. Hybrid pipelining the reduction delay difference between maximum minimum delays by narrowing gap each stage system. This yields narrow "computing cones" that could allow faster clocks to be run. first...

This paper will briefly review nanoelectronic challenges while focusing on reliability. We shall present and analyze a series of CMOS-based examples for addition starting from the device level moving up to gate, circuit, block level. Our analysis, backed by simulation results, comparing parallel serial shows that adders are more reliable also dissipating less. Their reliability can be improved using reliability-enhanced gates and/or other redundancy techniques (like e.g., multiplexing)....

In this paper we introduce a VLSI priority encoder that uses novel lookahead scheme to reduce the delay for worst case operation of circuit, while maintaining very low transistor count. The encoder's topmost input request has highest priority; descends linearly. Two design approaches are presented, one without and with scheme. For an N-bit encoder, circuit requires only 1.094 times number transistors Having 32-bit as example, is 2.59 faster than lookahead. 4.4 ns using 1-/spl mu/m scalable...

The content addressable memory (CAM) is a in which data can be accessed on the basis of contents rather than by specifying physical address. In paper, five novel dynamic ternary CAM cells with decoupled match lines are presented. A cell capable storing and matching three values: zero (0), one (1), don't care (X). proposed (DCAM) range number transistors from 6 n-type up to 10.5 n- p-type (one transistor shared between two cells). fast read operations enhancing performance system. Using...

In this paper different logic circuit families operating in the subthreshold region are analyzed. Their performance terms of power and speed particular interest. The study complements existing work that has reported static CMOS under body biasing schemes region. Further it offers assurances on noise margins with scaling going beyond 100 nm technology node. Simulations have been performed at 180 node using a 6 metal layer TSMC process. A tunable scheme allows bulk circuits to operate...

A VLSI implementation of a programmable pipelined router scheme for parallel machine interconnection networks is presented in this paper. The based on dynamic content-addressable memory (DCAM) that supports unique bit masking per entry. number required DCAM entries extremely small; it the same order as node degree (output ports). This, turn, makes possible to implement reduce physical size system. implemented with only six and half transistors (one transistor shared by two cells). We have...

Interest in subthreshold design has increased due to the emergence of systems that require ultra-low power and ever increasing leakage currents (now used drive logic). Subthreshold sacrifices speed for creating a clear divide between designing high power. It might be beneficial allow circuits operate super-threshold, depending on processing needs. In this paper, feasibility optimizing device sizes both above threshold operations is considered. addition body biasing techniques could...

Clock skew and clock distribution are increasingly becoming a major design concern in synchronous pipelined systems. We present novel high-speed hybrid wave-pipelined linear feedback shift register that manages by permitting the to travel with its associated data through pipeline. The has 8.34 times lower than of buffered is 1.2 faster.

In this paper three carbon nanotube FET based static memory cells are compared on read and write delays, energy consumption, performance under diameter variation corners. The is currently considered to be the possible ldquobeyond CMOSrdquo device due its1-D transport properties that include low carrier scattering ballistic transport. classified by their transistor count (6-, 7- 8-transistor cell.) Under a nominal of 1.51 nm, 8-T cell has lowest delay consumption 3.7 ps 0.348 fJ,...

In this paper different logic circuit families operating in the subthreshold region are analyzed. Their performance terms of power and speed particular interest. The study complements existing work that has reported static CMOS under body biasing schemes region. Further it offers assurances on noise margins with scaling going beyond 100 nm technology node. Simulations have been performed at 180 node using a 6 metal layer TSMC process. A tunable scheme allows bulk circuits to operate...

This paper explores low power reliable micro-architectures for addition. Power, speed, and reliability (both defect- fault-tolerance) are important metrics of system design, spanning device, gate, block, architectural levels. The analysis considers the needs future systems at supply voltages comparable to threshold (V/sub th/). Theoretical simulations show a decline speed advantages parallel adders when considering wire delays. These evaluations suggest that serial might do better (ultra)...

The Network-on-Chip (NoC) is emerging as a revolutionary methodology in solving the performance limitations arising out of long interconnects. Continued advancement NoC designs heavily dependent on ability to effectively communicate among constituent Intellectual Property (IP) blocks/Embedded cores, well manage/reduce energy dissipation. This paper presents low-latency, low-energy synchronization mechanism for Network Chip architectures, which enables network span system-on-chip (SoC) with...

In this study we present a metallic carbon nanotube (CNT) tolerant CNTFET memory. The proposed scheme includes number of uncorrelated (independent) CNTs in series to form CNTFETs provides tolerance CNTs. To increase driving capabilities parallel (correlated) transistors are used. addition spare columns used the memory array yield. An extremely high probability having functional can be obtained with modest semiconductor CNT (P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML"...

In this paper a novel hybrid wave-pipelined bit-pattern associative router is presented. A an important component in communication network systems. The (BPAR) allows for flexibility and can accommodate large number of routing algorithms. Wave-pipelining high performance approach which implements pipelining logic without using intermediate registers. study has been proposed implemented. Hybrid wave-pipelining the reduction delay difference between maximum minimum delays by narrowing gap each...

A novel ternary dynamic content addressable memory cell with coupled match lines is presented here. The CAM contains only four n-type transistors. This capable of storing and matching three states, hence the term ternary; these states are: zero (0), one (1) don't care (X). Circuit simulations show that our performs all basic operations (read, write match) at a good speed. In order to use proposed in array, we developed cut-off scheme deal coupling.

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Abstract Distance Education Program in Electrical Engineering: TV Broadcasting, WebEx and Laboratory ManagementTraditional engineering programs are taught a class setting, accompanied with laboratoryexercises that complement lecture reinforce theory. This is the ideal format, as students haveeasy access to both faculty laboratories. Many times, however, place-bound inlocations where they do not have institutions offering programs.Furthermore, degrees expensive opening one requires...

The majority of digital circuits/systems primarily use synchronous clocking methodology. With clock distribution networks dissipating ever more power and the wire delays expected to become dominant, there has been increased activity provide alternative solutions. This paper explores some potential methods for reducing global interconnect improving throughput between communicating modules. Analysis classical repeater insertion is performed a wave-pipelined scheme that addresses shortfalls...

Advancement in silicon technology has led to miniaturization of devices, scaled power supply voltages and faster transistor switching speeds just name a few. Along with these improvements came issues such as threshold voltage scaling, interconnect delays, sensitivity variations, increased dissipation. Device also seen rise battery-operated electronic devices very stringent energy requirements. Clearly, dissipation is already major design challenge highly integrated systems. Leakage currents...

Refreshing dynamic circuits must be carried out before stored voltages reach unacceptable levels. In this paper we present CMOS circuitry that can used to sense the integrity of data, provide timely refreshing these and high performance. Differential amplifiers are difference between a degrading voltage reference voltage. This gets converted single-ended output which serves as refresh trigger. Memory arrays test beds verify functionality effectiveness circuits. The considered in suitable for...

Advancement in technology has seen correspondence education evolve into distance and eLearning. A large number of universities across the United States America have established some form and/or eLearning an effort to offer opportunities many people aspiring obtain education, but with limitations when it comes accessing institutions higher learning. Most states specialized high speed networks intended specifically for use enhance make accessible virtually anyone inclination attend school. The...