A5101989053- Radiation Effects in Electronics
- Advanced Neural Network Applications
- VLSI and Analog Circuit Testing
- Integrated Circuits and Semiconductor Failure Analysis
- Advanced Memory and Neural Computing
- Semiconductor materials and devices
- Human Pose and Action Recognition
- Video Surveillance and Tracking Methods
- Advanced Image and Video Retrieval Techniques
- Adversarial Robustness in Machine Learning
- Parallel Computing and Optimization Techniques
- Domain Adaptation and Few-Shot Learning
- Distributed systems and fault tolerance
- Silicon Carbide Semiconductor Technologies
- Photonic and Optical Devices
- CCD and CMOS Imaging Sensors
- Advanced Image Processing Techniques
- Fire Detection and Safety Systems
- Machine Learning and ELM
- Ferroelectric and Negative Capacitance Devices
- COVID-19 diagnosis using AI
- Low-power high-performance VLSI design
- Interconnection Networks and Systems
- Network Security and Intrusion Detection
- Neural Networks and Applications
Jilin University of Chemical Technology
2025
University of Chicago
2017-2024
Beihang University
2019-2024
Heilongjiang University
2022-2024
Shijiazhuang University
2023-2024
California Institute of Technology
2024
Xi’an University of Posts and Telecommunications
2024
University of Illinois Chicago
2019-2023
Anhui University of Finance and Economics
2021
Sinopec (China)
2011-2020
Image super-resolution (SR) has attracted increasing attention due to its widespread applications. However, current SR methods generally suffer from over-smoothing and artifacts, most work only with fixed magnifications. This paper introduces an Implicit Diffusion Model (IDM) for high-fidelity continuous image super-resolution. IDM integrates implicit neural representation a denoising diffusion model in unified end-to-end framework, where the is adopted decoding process learn...
CASP, Concurrent Autonomous chip self-test using Stored test Patterns, is a special kind of where system tests itself concurrently during normal operation without any downtime visible to the end-user. CASP consists two ideas: 1. Storage very thorough patterns in non-volatile memory; and, 2. Architectural and system-level support for autonomous testing one or more cores multi-core stored patterns, with operation, bringing down entire system. enables design robust systems built-in features...
The dry impinger method, the indirect dilution and direct method can be used to measure condensable particulate matter (CPM) emissions. We tested these methods in determining CPM emissions from typical stationary sources China found that concentrations measured by are much higher than those two regardless of type source. soluble gases (e.g., SO2, HCl, NH3) partially absorbed solutions main reason for overestimation concentrations. This is supported detecting more water-soluble ions SO42–,...
Long error detection latency, the time elapsed between occurrence of an caused by a bug and its manifestation as system-level failure, is major challenge in post-silicon validation robust systems. In this paper, we present new technique called Quick Error Detection (QED), which transforms existing tests into that significantly reduce latency. QED transformations allow flexible tradeoffs coverage, complexity, can be implemented software with little or no hardware changes. Results obtained...
The prospect of system failure has increased because device and chip-level effects in the late CMOS era. In this article, authors present novel system-level architecture design innovations to cope with these lifetime reliability challenges. At nanometer-scale geometries, several hardware mechanisms, which were largely benign past, are becoming visible at level. Moreover, recent studies indicate that, depending on application, failures can be significant contributors overall rates.Design...
Today's mainstream electronic systems typically assume that transistors and interconnects operate correctly over their useful lifetime. With enormous complexity significantly increased vulnerability to failures compared the past, future system designs cannot rely on such assumptions. For coming generations of silicon technologies, several causes hardware reliability failures, largely benign in are becoming significant at level. Robust design is essential ensure perform despite rising...
This paper presents the Quick Error Detection (QED) technique for systematically creating families of post-silicon validation tests that quickly detect bugs inside processor cores and uncore components (cache controllers, memory on-chip interconnection networks) multicore system on chips (SoCs). Such quick detection is essential because long error latency, time elapsed between occurrence an due to a bug its manifestation as observable failure, severely limits effectiveness traditional...
We present a resilience analysis framework, called FIdelity, to accurately and quickly analyze the behavior of hardware errors in deep learning accelerators. Our framework enables starting from very beginning design process ensure that reliability requirements are met, so these accelerators can be safely deployed for wide range applications, including safety-critical applications such as self-driving cars.Existing techniques suffer following limitations: 1. general-purpose achieve accurate...
The large pre-trained vision transformers (ViTs) have demonstrated remarkable performance on various visual tasks, but suffer from expensive computational and memory cost problems when deployed resource-constrained devices. Among the powerful compression approaches, quantization extremely reduces computation consumption by low-bit parameters bit-wise operations. However, ViTs remain largely unexplored usually a significant drop compared with real-valued counterparts. In this work, through...
The recent detection transformer (DETR) has advanced object detection, but its application on resource-constrained devices requires massive computation and memory resources. Quantization stands out as a solution by representing the network in low-bit parameters operations. However, there is significant performance drop when performing quantized DETR (Q-DETR) with existing quantization methods. We find that bottle-necks of Q-DETR come from query information distortion through our empirical...
Analytical Target Cascading (ATC) is an effective decomposition approach used for engineering design optimization problems that have hierarchical structures. With ATC, the overall system split into subsystems, which are solved separately and coordinated via target/response consistency constraints. As parallel computing becomes more common, it desirable to separable subproblems in ATC so each subproblem can be concurrently increase computational throughput. In this paper, we first examine...
Deep neural network (DNN) training workloads are increasingly susceptible to hardware failures in datacenters. For example, Google experienced "mysterious, difficult identify problems" their TPU systems due [7]. Although these particular problems were subsequently corrected through significant efforts, they have raised the urgency of addressing growing challenges emerging from impacting many DNN workloads.
Target-driven visual navigation presents great potentials in scientific and industrial fields. It takes the target environment observations as input. However, during training, we found that agent sometimes got stuck specific locations. Based on analysis information from a novel causal perspective, one of most critical hurdles is neglect confounders environments, which often leads to spurious correlations. Mitigating confounding effect helps discover real causality therefore are taken into...
Binary neural networks (BNNs) have received ever-increasing popularity for their great capability of reducing storage burden as well quickening inference time. However, there is a severe performance drop compared with {real-valued} networks, due to its intrinsic frequent weight oscillation during training. In this paper, we introduce Resilient Neural Network (ReBNN) mitigate the better BNNs' We identify that mainly stems from non-parametric scaling factor. To address issue, propose...
Virtualization-Assisted concurrent, autonomous Self-Test, or VAST, enables a multi-/many-core system to test itself, concurrently during normal operation, without any user-visible downtime. Such on-line self-test is required for large-scale robust systems with built-in support circuit failure prediction, detection, diagnosis, and self-healing. The main idea behind VAST hardware software co-design of features in through integration of: 1. architecture, 2. virtualization software, and, 3....
We identify an important asymmetry in physical DRAM cells that can be utilized to prevent RowHammer attacks by adding 18 lines of code modify the OS memory allocator. Our small modification has a powerful impact on RowHammer's ability bypass protection mechanisms and achieve successful attack. Specifically, we two types cells: true-cells anti-cells. In true-cell, leaking capacitor will induce '1'->'0' error, while anti-cells, errors flow from '0'->'1'. then create cell-type-aware allocation...
Analytical target cascading (ATC) is an effective decomposition approach used for engineering design optimization problems that have hierarchical structures. With ATC, the overall system split into subsystems, which are solved separately and coordinated via target/response consistency constraints. As parallel computing becomes more common, it desirable to separable subproblems in ATC so each subproblem can be concurrently increase computational throughput. In this paper, we first examine...