In this paper, we propose a low-power area-efficient redundant flip-flop for soft errors, called DICE-ACFF. Its structure is based on the reliable DICE (Dual Interlocked storage CEll) and ACFF (Adaptive-Coupling Flip-Flop). It achieves lower power at data-activity. We designed DICE-FF DICE-ACFF using 65 nm conventional bulk thin-BOX FD-SOI (Silicon Thin-BOX, SOTB) processes. area twice as large DFF. As dissipation, than DFF below 20% data activity. When activity 0%, its half of error rates...

A layout structure to avoid upsets due Multiple Cell Upsets (MCUs) is proposed for rad-hard dual-modular Flip-Flops (FFs) called BCDMR (Bistable Cross-coupled Dual-Modular Redundancy) by separating critical components. We have fabricated a 65 nm chip including 30 kbit FF arrays on twin-well and triple-well structures. High-energy broad-spectrum neutron irradiations reveal that no soft error observed up 100 MHz in the twin-well, but some errors are triple well. The sensitive MCUs because...

We propose a Bistable Cross-coupled Dual Modular Redundancy (BCDMR) Flip-Flop to enhance soft-error immunity. It is based on BISER FF but its bistable cross-coupled structure enhances immunity without any area, delay and power overhead. fabricated 65 nm LSI including 60,480 bit shift registers with the BCDMR structures. Experimental results using α-particles reveals that of enhanced by 150 × at 160 MHz clock frequency compared BISER.

Soft-error tolerance depending on threshold voltage of transistors was evaluated by α -particle, heavy-ion, and neutron irradiation. Three chips were fabricated, one embeds low-threshold general-purpose (GP) the others embed high-threshold low-power (LP) in a 65 nm fully depleted silicon insulator (FDSOI) process. There few errors LPDFFs (DFFs with LP transistors). Error probability (EP) 99.88% smaller than that GPDFFs GP transistors) particles. Average cross sections (CSs) heavy ions 50%...

In this paper, we propose radiation-hardened flip-flops (FFs) based on the adaptive coupling FF with low dynamic power and short delay overhead in a 65-nm fully depleted silicon insulator process. We designed four FFs composed of master latch pMOS pass-transistors to reduce time slave stacked transistors for high soft-error tolerance. evaluated radiation hardness newly using TCAD simulations, α particle test, neutron irradiation test. simulations show that proposed structure has enough...

We measured neutron-induced Single Event Upsets (SEUs) and Multiple Cell (MCUs) on Flip-Flops (FFs) in a 65 nm bulk CMOS process. Measurement results show that MCU / SEU is up to 23.4% exponentially decreased by the distance between latches FFs. rates can drastically be reduced inserting well-contact arrays The number of MCUs from 110 1 array under power ground rails.

This paper presents a three-level gate driver for GaN HEMTs (Gallium Nitride High Electron Mobility Transistors) high false turn-on tolerance and low reverse conduction loss during both dead time at turn-off. The proposed reduces the by clamping between source terminals only time. It has capacitor which works as negative voltage prevents from phenomenon. operates with single PWM (Pulse Width Modulation) output signal. is implemented on 48V-to-12 V synchronous rectifier buck (SR-buck)...

We propose a single event transient (SET) pulse width measurement circuit using propagation-induced shrinking on clock buffer chain. It achieves the resolution of less than 1ps since target chain is directly connected to capture FFs. Experimental results spallation neutron beam accelerated test show SET widths are exponentially-distributed and number SETs longer 350 ps reduced 9% by inserting tap-cells closely. The rate 23x smaller SEU

The RCD (Resistor-Capacitor-Diode) snubber is usually designed without considering which wiring inductance seriously affects circuit behaviors, although the influence appears significantly at high-frequency operation. We investigate an optimal design of for MHz-switching SiC-MOSFETs location parasitic inductance. mechanism ringing induced by inductance, and suppression are also discussed. near gate source terminals should be minimized. drain must considered to snubber.

We propose SLCCFF which is a radiation hardened non-redundant flip-flop for an SOI process. The has the stacked structure to prevent soft errors on processes while maintaining smaller delay and power overhead than conventional FFs. Energy product of 86% FF. fabricate test chip in 65 nm thin BOX FDSOI process measured error rates SLCCFF, FF standard DFF by neutron irradiation α particles. Experimental results show that about 27x stronger at 0.4 V supply SOTB It 1080x compared with bulk

We propose a low-power redundant flip-flop to be operated with high reliability over 1 GHz clock frequency based on the (ACFF) and highly-reliable (BCDMR) flip-flops. Its power dissipation is almost equivalent transmission-gate FF at 10% data activity while paying 3 × area penalty. Experiments by α-particle neutron irradiation reveal its operations no error 1.2 V GHz. measured five different process corner chips α irradiation. Soft rates are in these chips.

We propose a low surge voltage and fast speed gate driver with switched capacitor circuit for Silicon-Carbide (SiC) MOSFET. Because of the high switching frequency SiC MOSFET, becomes serious problem which cause loss may break There is trade-off between speed. It hard to fulfill both them at same time by using conventional drivers. With circuit, proposed can reduce 17.2% 8.4% turn-off transient. Compared drivers without generate negative gate-source any isolated power supply.

We found that specific pairs of pMOS and nMOS transistors in dual interlocked storage cell flip flop (DICEFF) become sensitive to soft errors by device simulations. propose several layout structures can improve soft-error tolerance with additional 39%-46% area overhead. evaluated a D-type FF (DFF) DICEFFs 65-nm bulk process heavy ions. Our experimental results showed the DICEFF has more than 300× better DFF Kr (LET 40.3 MeV·cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML"...

We evaluated soft-error tolerance by heavy-ion irradiation test on three-types of flip-flops (FFs) named the standard FF (STDFF), dual feedback recovery (DFRFF), and DFRFF with long delay (DFRFFLD) in 22 65 nm fully-depleted silicon insulator (FD-SOI) technologies. The guard-gate (GG) structure mitigates soft errors. A single event transient (SET) pulse is removed C-element signal delayed GG structure. DFRFFLD increases adding two more inverters as elements. investigated effectiveness nm. In...

We propose a radiation-hardened flip-flop (FF) combined with transient-fault tolerant (TFT) structure and fabricated test chips in 65 nm FD-SOI technology. Heavy ion irradiation tests show that the cross section of proposed TFT FF is about two orders magnitude lower than standard when linear energy transfer irradiated heavy ions 69 MeV-cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /mg. The achieves high error tolerance 35% area, 15%...

We measured soft error rates on DICE latches with different layout structures in order to characterize multiple node upsets. Measurement results showed that the rate of weakest latch was 1/3 a standard FF, which has closest distance between pMOSFETs and nMOSFETs. In contrast, smallest is about 1/100 FF.

We propose SLCCFF which is a radiation hardened non-redundant flip-flop in 65 nm SOTB (Silicon On Thin BOX) process. measured its soft error rates by neutron irradiation. has the stacked structure to prevent errors on SOI processes while maintaining smaller delay and power overhead than conventional FFs. Experimental results show that about 27x stronger standard DFF at 0.4V supply It 1000x compared with bulk

Three different latch structures are fabricated in a 65 nm FDSOI process. We evaluate soft-error tolerance of latches by device simulations and particle, neutron, heavy-ion irradiation tests order to identify which transistor type is dominant cause soft errors. The structure including an inverter with stacked NMOS unstacked PMOS transistors has enough against errors up heavy ions 40 MeV-cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>...

Technology scaling increases the role of charge sharing and bipolar effect with respect to multiple cell upset. We analyze contributions distance well-contact density suppress MCU by device-level simulations neutron experiments. Device simulation results reveal that ratio SEU exponentially decreases increasing between redundant latches. is suppressed when well contacts are placed Experimental also show cells. effectively contacts.

Measuring bias temperature instability (BTI) by ring oscillators (ROs) is frequently used. However, the performance of a semiconductor chip fluctuated dynamically due to bias, and etc. BTI-sensitive -insensitive ROs are implemented in order extract BTI-induced degradation without temporal fluctuation factors. A test including those 840 was fabricated 65 nm process. successfully measured subtracting results BTI-insensitive from ones. Extraction useful any supply voltage. Performance NMOS PMOS...

We conducted a study on the frequency dependence analysis of soft error rates using flip-flops (FF) and inverters. The measurement circuit consists scan FFs By irradiating with alpha particles while clock was running, were measured. results showed that errors caused by inverters almost negligible. On other hand, decreased as operating increased. time window when FF cannot capture its input until rising edge is fixed at any frequency. As result, increases, ratio where are not captured to in...

This paper analyzes how body bias and BOX region thickness affect soft error rates in 65-nm SOTB (Silicon on Thin BOX) 28-nm UTBB (Ultra Body FD-SOI processes. Soft errors are induced by alpha-particle neutron irradiation the results then analyzed Monte Carlo based simulation using PHITS-TCAD. The alpha-particle-induced single event upset (SEU) cross-section neutron-induced rate (SER) obtained consistent with measurement results. We clarify that SERs decreased response to an increase for...

We evaluated soft-error tolerance by neutrons and heavy ions on four types of flip flops (FFs) called D-type flop (DFF), guard-gate FF (GGFF), feedback recovery (FRFF), dual FRFF (DFRFF) in a 65-nm thin buried oxide (BOX) fully depleted silicon insulator (FDSOI). has structure only the master latch. GGFF DFRFF have both slave latches. The resolves single-event transient (SET) pulse delaying it through guard gate. smaller area shorter delay overheads than GGFF. revealed that high low-linear...

We propose a radiation-hardened Flip-Flop (FF) with stacked transistors based on the Adaptive Coupling (ACFF) low power consumption in 65 nm FDSOI process. The slave latch ACFF is much weaker against soft errors than master latch. design several FFs or latches to mitigate errors. investigate radiation hardness of proposed by α particle and neutron irradiation tests. have higher conventional DFF ACFF. Neutron tests revealed no error AC Slave-Stacked FF (AC_SS FF) which has only also heavy ion...