A5024380485- Interconnection Networks and Systems
- Parallel Computing and Optimization Techniques
- Photonic and Optical Devices
- Low-power high-performance VLSI design
- Embedded Systems Design Techniques
- VLSI and FPGA Design Techniques
- Electronic and Structural Properties of Oxides
- VLSI and Analog Circuit Testing
- Semiconductor materials and devices
- Advanced Electron Microscopy Techniques and Applications
Barcelona Supercomputing Center
2021-2024
Universitat Politècnica de Catalunya
2021-2024
Instituto Politécnico Nacional
2023
The RISC-V open Instruction Set Architecture (ISA) has proven to be a solid alternative licensed ISAs. In the past 5 years, plethora of industrial and academic cores accelerators have been developed implementing this ISA. paper, we present Sargantana, 64-bit processor based on that implements RV64G ISA, subset vector instructions extension (RVV 0.7.1), custom application-specific instructions. Sargantana features highly optimized 7-stage pipeline out-of-order write-back, register renaming,...
The integration of many processing elements per die makes it more difficult to provide low latency in the Network-on-Chip (NoC). Multihop bypass proposals, such as SMART, attack this problem by allowing flits skip multiple routers path a single cycle, drastically reducing while preserving regular tiled layout. However, multihop are complex and relatively different from traditional NoC routers, since they rely on global broadcast signals allocation mechanisms. Additionally, maximum number...
In recent years, numerous multicore RISC-V platforms have emerged. Within the ecosystem, Networks-on-Chip (NoCs) such as OpenPiton are employed in designs that aim to scale a large number of cores. This paper presents set extensions and optimizations for high-performance manycores. The key contributions enabling multiple memory controllers, supporting router bypassing NoC concentration, adding support configurable cache sizes block sizes. On 64-core manycore architecture, these new features...
This paper describes the Sargantana System on chip (SoC), a 64-bit RISC-V single core processor designed by number of academic institutions and manufactured in 22 nm FDSOI technology: BSC, UPC, UB, UAB, CIC-IPN IMB-CNM (CSIC). The SoC includes as well as, among other components, Phase Locked Loop (PLL) operating up to 2 GHz, interfaces HyperRAM Serdes 8 Gbps. has demonstrated experimental correct operation at 800 MHz.
This article enhances the SynFull NoC simulation framework to support RTL simulations with higher accuracy and speed.