A5056130525- Semiconductor materials and devices
- Advancements in Semiconductor Devices and Circuit Design
- Integrated Circuits and Semiconductor Failure Analysis
- Thermal properties of materials
- Silicon Carbide Semiconductor Technologies
- Electronic Packaging and Soldering Technologies
- 3D IC and TSV technologies
- Ferroelectric and Negative Capacitance Devices
- Semiconductor materials and interfaces
- Thermography and Photoacoustic Techniques
- Electrostatic Discharge in Electronics
- Industrial Vision Systems and Defect Detection
- Microwave Engineering and Waveguides
- Reliability and Maintenance Optimization
- VLSI and Analog Circuit Testing
- Software Reliability and Analysis Research
- Copper Interconnects and Reliability
- Radio Frequency Integrated Circuit Design
GlobalFoundries (United States)
2014-2022
University of Modena and Reggio Emilia
2020
IMEC
2020
TU Wien
2020
New Jersey Institute of Technology
2017-2018
GlobalFoundries (Cayman Islands)
2017
Performance enhancement is critical for offering competitive CMOS solutions advanced technology nodes. To fully leverage performance elements the device reliability impact needs to be comprehended on circuits like SRAM and ring-oscillators. We reaffirm that time-zero BTI induced stochastic variation are most while logic such as ring-oscillators focus mean degradation. In addition we explore of self-heating correlation circuit degradation FinFET architecture.
This paper describes three different measurement methodologies for the electrical characterization of FinFET self-heating at wafer-level. Finite element simulations heat transport are used to interpret heater-sensor temperature gradients and validate measurements. The sensor types were designed use threshold voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> ) an adjacent FET, forward bias...
This paper discusses the impact of self-heating (SH) on ring-oscillator (RO) reliability and its correlation to hot carrier (HC) degradation. We show that HC degradation modulation due SH is only significant for logic PFETs at highly accelerated dc conditions. these effects are greatly reduced moderate acceleration. By stressing ROs extreme conditions, we does not affect RO
Ring-Oscillator (RO) are most suitable to investigate the reliability of digital CMOS circuits operating up GHz frequencies as a good correlation has been observed between RO degradation and Product Fmax degradation. In addition, testing can be performed with similar equipment used for discrete device characterization. this work, we discuss role BTI/HCI contribution in compare contributions NFET PFET devices. To decouple contribution, AC characterization on devices is conducted correlated...
We present a hierarchical methodology using combination of ab-initio phonon scattering, electron transmission, and multi-scale finite element simulations to accurately model process specific material physics component level self-heating in FinFET technologies. The framework is applied explain key heat transfer pathways thermal resistance FinFETs, interconnects integrated precision resistors. Excellent agreement with measurements its dependence on technology demonstrated across many device...
Self-Heating effects are going to be of increasing significance in future nodes. Understanding self-heating measurement results and its accuracy is vital importance. In this paper we show for the first time through that ambient temperature can affect by up 70%. Through a series measurements at different temperatures dissipated power, Si fin has more dominant effect heat transport varying thermal conductivity should taken into account.
Standard CMOS reliability has been focused on digital applications and the user profiles associated with these products. However, emerging in mobility, automotive, communication networks data centers require additional, more rigorous specifications. For applications, devices operate beyond typical safe operation area (SOA) mostly because large drain biases are applied during normal operation. In this situation, off-state TDDB could be a concern it must considered product design. study, we...
A novel anti-fuse memory array is presented in this paper featuring one-capacitor (1C) per bit-cell design and fully compatible with 14nm FinFET CMOS technology. The rectifying I-V characteristics of the metal-insulator-semiconductor (MIS) structure after programming prevents sneak current cross-point array, therefore no need for select transistor each cell. Thus enables smallest reported area measuring 0.036 μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML"...
Building in reliability is critical during technology development, as we continue scaling or incorporating additional functionality. In this paper Front End Of Line methodologies (FEOL) for DC and AC degradation with correlation to RO/SRAM/Logic are presented. Self-Heating Variability characterization together inline monitoring discussed commercial automotive applications.
This paper describes three different measurement methodologies for the electrical characterization of FinFET self-heating at wafer-level. The sensor types were designed to use threshold voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> ) an adjacent FET, forward bias xmlns:xlink="http://www.w3.org/1999/xlink">D</sub> pn-junction or gate resistance (R xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> device itself. We report...
This paper discusses the impact of self-heating (SH) on ring-oscillator (RO) reliability and its correlation to hot carrier (HC) degradation. We show that HC degradation modulation due SH is only significant for logic PFETs at highly accelerated conditions. these effects are greatly reduced moderate acceleration. By stressing ROs extreme conditions, we does not affect RO
This paper presents a systematic methodology by thermal characterization and simulation of 3-FET stacked K/Ka-band class-AB power amplifier built on GLOBALFOUNDRIES 45nm SOI process. A detailed temperature profile is obtained in the FEOL BEOL stacks first using special gate Kelvin measurement structures novel metal sensor stack at several Mx layers (M <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sub> -M...
Wafer level reliability of TSV has been studied with respect to FEOL (Front end line) and BEOL (Back aspects. keep out zone (KoZ) study done varying gate length width transistor. Voltage ramp stress (VRS) analysis by voltage for different KOZ both SG EG oxide devices found not significant impact device performance. Testing is thick thin (50um) wafer little effect due thinning. tests are at 125 deg C a 50um wafer, new methodology probing the from back side through carrier demonstrated....
The understanding of self-heating effects and heat dissipation in semiconductor devices is a necessary element for the accurate modeling prediction reliability indicators. Unfortunately, small dimensions, complex device structures, presence thin-oxidized interfacial layers make it impractical to determine these quantities experimentally. In this work, we calculate electrical conductances (<inline-formula> <tex-math notation="LaTeX">${\sigma }$ </tex-math></inline-formula>), electronic...
• The deep collaboration between the experimental and simulation groups is needed. This require that: Experimental should previously know what kind of information simulations could provide need. Simulation type can provide. We need adapt level to we are looking for.
This work presents various device self-heating temperature sensing techniques and discusses their application in reliability projection. Details of sensor design, technology choice, layout ambient impact on measurement results are discussed. The sensors produce excellent which were confirmed through TCAD thermal simulation. Self-heating was studied by varying the number fins per active region proximity to heater investigated. While most data presented here is FinFET learning applicable...
In this work, we explore the effect of different IMD deposition tools on occurrence early electromigration (EM) failure. The failure is revealed by fast Wafer Level Reliability (fWLR) method. It found that under same embedded scheme (i.e. HDP FSG and then TEOS USG), initial film condition main cause for fWLR-EM deteriorates subsequent USG stress imposes metal layers. This also confirmed Package EM (PLR-EM). Moreover, understanding reliability risk caused quality, performed recipe improvement...
The endless demand for high performance and low power CMOS devices at extremely scaled cell dimensions led the semiconductor industry to migrate FinFET structures. This evolution has brought higher integration complexity forced reliability engineers be aware of interrelation among process conditions affecting electrical degradation failure. In this work, major steps which impact FEOL/MOL are discussed, guidance is provided reliability-aware design.
High consequence ICs and discrete components: Medical implantable devices, life-support systems, aeronautics, automotive safety to self driving cars, satellites, defense, etc. Low volume: Manufacturers of unique parts with a small fabs Small companies that can buy only few wafer lots from highvolume foundry. Product reliability evaluation qualifications are based on low volume, hence, statistical sample sizes. How develop effective screening weak parts? verify the required reliability?
Plasma induced charging is known to cause gate oxide and MIM capacitor reliability degradation. However, the impact of plasma on metal/via rarely reported. This paper highlights importance built-in-reliability during design via connections poly. Large area per shown resistance reliability. Thus, it recommended ground these or be less than 600um <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> minimize impact.