A5009267540- Advancements in Semiconductor Devices and Circuit Design
- Low-power high-performance VLSI design
- Smart Agriculture and AI
- Semiconductor materials and devices
- Quantum-Dot Cellular Automata
- Spectroscopy and Chemometric Analyses
- Analog and Mixed-Signal Circuit Design
- Industrial Vision Systems and Defect Detection
- Fire Detection and Safety Systems
- Smart Systems and Machine Learning
- Horticultural and Viticultural Research
- Welding Techniques and Residual Stresses
- Ferroelectric and Negative Capacitance Devices
- Plant and soil sciences
- Advanced Memory and Neural Computing
- Integrated Circuits and Semiconductor Failure Analysis
- Additive Manufacturing Materials and Processes
- Plant Disease Management Techniques
- Date Palm Research Studies
- Advanced Chemical Sensor Technologies
- Plant Virus Research Studies
Chitkara University
2022-2024
Achieving low power consumption along with delay for adiabatic logic circuits is challenging in CMOS technology. This study has presented an Efficient Charge Recovery Logic (ECRL) technique based 2:1 MUX designed using FinFET 18 nm A comparative analysis of the design been performed MUX. Further parametric terms average dissipation, propagation delay, Power Delay Product (PDP), and Energy (EDP) are this work. All considered parameters have analyzed 0.5 V, 0.7 0.9 1. 1V. The results show that...
This research paper introduces a novel methodology that employs Convolutional Neural Networks (CNNs) and Support Vector Machines (SVMs) to classify grapevine leaf diseases. A complete dataset consisting of photos leaves exhibiting different illnesses healthy conditions was gathered subjected preprocessing techniques assure consistency improve the resilience model. The design Network (CNN) comprised three convolutional layers, succeeded by max-pooling culminated in solitary fully connected...
In the VLSI design circuit, average power dissipation is a very common source of concern. This paper aims to reduce and other parameters that are performed in this notably propagation delay, EDP (energy delay product), PDP (Power product). These two technologies have been compared based on 2:1 MUX using Differential Cascode Voltage Switch Logic (DCVSL) Modified (MDCVSL) has presented with FinFET 18nm technology. The results show values Power Delay Product (PDP) Energy for DCVSL approach at...
The cultivation of wheat, as a fundamental cereal crop, is confronted with substantial challenges posed by range diseases, which have profound influence on agricultural output and the overall stability food supply. This study introduces new methodology that utilizes Convolutional Neural Networks (CNN) Support Vector Machines (SVM) to achieve precise diagnosis classification wheat illnesses analyzing leaf photos. research starts rigorous phase gathering data, performing preprocessing tasks,...
By combining Convolutional Neural Network (CNN) and Support Vector Machine (SVM) approaches, this study presents a new way to forecast which diseases would strike walnut leaves. The first of the study's four stages is careful gathering preparation data create varied consistent dataset. next step train model extract features using convolutional neural network architecture with three max-pooling layers, one fully connected layer, layers. This works in tandem support vector machines (SVMs)...
ABSTRACT This work presents a FinFET‐based stable, and low‐power consuming static random access memory (SRAM) bit‐cell that used eight transistors. The performance parameter of proposed feedback‐cutting 8T (FC8T) is compared with four pre‐published cell circuits, i.e., 6T, read‐decoupled 8T(8TRD), Schmitt‐trigger based 10T (10TST), Schmitt‐trigger‐based modified 10 T (10TMST). write power in design reduced by 1.36×/1.32×/1.88×/1.47× to 6T/8TRD/10TST/10TMST cells. read stability improved...
Pass Transistor Logic characterizes several logic families by eliminating redundant MOS transistors from the CMOS digital architecture. This can be effectively employed to construct area and power efficient circuits. At ultra-scaled technology nodes, performance of circuits based on technique gives degraded performance. In this work, one-bit adder circuit using push-pull pass transistor (PPL) energy economized (EEPL) approaches are designed. FinFET 18nm has been used perform comparative...
The primary concerns in VLSI circuit design technology are usually power usage and propagation delay optimization. In this paper, we have proposed energy-economized pass-transistor (EEPL) techniques complementary logic (CPL) based on 2:1 multiplexer (MUX) using FinFET 18 nm technology. result shows the value of Power Delay Product (PDP) for EEPL at 1.2 V is <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$1142.04\times 10^{-4}$</tex> (J), 1...
In the context of paddy leaf diseases, this study thoroughly assesses disease classification performance. Brown Spot Disease, Blasting Sheath Blight, Bacterial Leaf and Scald are only a few types evaluated in using essential metrics, including Precision, Recall, F1-Score. Disease achieved 95.24% Precision value, demonstrating model's accuracy making correct predictions. Scald's Recall value is 93.65%, success identifying true positives. Blight's F1-Score 92.52% exemplifies study's all-around...
Implantable electronics demand for ultra-low power techniques at nanometer regime. Due to limitations of CMOS technology new logic circuit using next generation devices are required be developed. In this work, FinFET based one-bit adder circuits designed Complementary Technique (CFT) and Pass Transistor Logic (CPTL) in 18 nm technology. The results show values Power Delay Product (PDP) Energy (EDP) CFT 6905. <tex xmlns:mml="http://www.w3.org/1998/Math/MathML"...
Pass Transistor Logic characterizes many logic families for the efficient design of digital circuits used in low-power electronics. can be efficiently area and power-efficient by removing redundant MOS transistors CMOS design. The technology-based suffer from performance degradation at ultra-scaled technology nodes. We this work have designed one-bit adder deploying pass transistor logics (PTL) lean integration with (LEAP) techniques. comparative analysis these two techniques based has been...
The most significant challenge in designing adders using the gate diffusion input (GDI) technology is minimizing anticipated area, power consumption, and propagation delay. In this article, we have compared both Half Adder (HA) Full (FA) circuits GDI technique. After simulation, it was determined that HA circuit performed better terms of power, delay, delay product (PDP), energy-delay (EDP), while FA consumed a larger area for its design. PDP at 1 V $2.237\times 10^{-16}{\mathrm{J}}$, 0.9...
A worldwide crop, sunflowers are subject to illnesses that can reduce productivity and quality. Agriculture needs early precise disease diagnosis control economic losses. We present a new sunflower illness classification method using CNNs SVMs. The study involves four primary phases. initially collected leaf photos of healthy diseased leaves, including Alternaria blight, Downy mildew, Phoma Verticillium wilt. Resizing, contrast modification, color improvement improve dataset quality...