Traditional synthesis techniques optimize CMOS circuits in two phases: i) logic minimization and ii) library mapping phase. Typically, the structures sizes of gates are chosen to yield good results over many blocks or even for an entire chip. Consequently this approach precludes optimal design individual which may need custom structures. The authors present a new transistor level technique that optimizes both structurally size-wise. is independent hence can explore space much larger than...

Cross-coupled noise analysis has become a critical concern in VLSI design. Typically, makes the assumption that all aggressing nets can simultaneously switch same direction. This creates worst-case pulse on victim net often leads to false violations. In this paper, we present new approach uses logic implications identify maximum set of aggressor inject under constraints circuit. We propose an efficiently generate from transistor-level description and propagate them circuit using ROBDD...

Cross-coupled noise analysis has become a critical concern in VLSI design. Typically, makes the assumption that all aggressing nets can simultaneously switch same direction. This creates worst-case pulse on victim net often leads to false violations. In this paper, we present new approach uses logic implications identify maximum set of aggressor inject under constraints circuit. We propose an efficiently generate from transistor-level description and propagate them circuit using ROBDD...

Negative bias temperature instability (NBTI) has become a primary mechanism that degrades performance of integrated circuits. It is well known NBTI impacts pMOS transistors during circuit operation, and the degradation occurs when transistor in conducting state. So, accurate analysis requires logic states. Degradation specific depends on part lifetime, which this under stress, other words, stress probability. In paper, we propose correct algorithm calculating probability for every complex...

A bottom-up circuit clustering step is one of the most significant steps in reconfigurable systems-on-chip design flow. Qualitative provides efficiency subsequent placement and routing steps. The goals are following: a) achieving high density by minimizing number clusters; b) decreasing time delays localizing time-critical connections within a cluster using fast local resources. There several popular solutions to these issues such as partitioning algorithms, heuristic algorithms. In this...

The paper considers the hierarchical two-level routing method for island style reconfigurable systems-onchip.The proposed approach can be successfully used field programmable gate arrays and systems-onchip also.The modified PathFinder algorithm is both global detailed (switchbox) routing.The special rebalancing technique to fasten reduce resulting interconnect paths.Its impact was tested analyzed.The particular attention paid rules switchbox route graphs generation as a part of mixed graph...

Reconfigurable system-on-chip (RSoC) is an integrated circuit that contains reconfigurable logic blocks and hard IP cores, such as microprocessors, RAM, LVDS, multipliers, etc. For successful RSoC design one needs a high-quality CAD system implementing new multilevel placement routing approaches take into account the natural hierarchy of devices. Placement most important complex stages in flow impacts main characteristics digital circuits. We developed two-level algorithm for initial...

The paper presents some algorithmic improvements to accelerate the routing stage for FPGA. One of main advantages FPGA is high development speed; thereby importance efficient computer-aided design tools modern hard overestimate. placement and stages are crucial performance, meanwhile they take up a significant part time. investigated base algorithm modified Pathfinder mixed resources graph. popular iterative negotiation-based router acting on principle eliminating nets congestions. Due...

High-performance digital circuits are facing increasingly severe noise problems due to cross-coupled injection. Traditionally, analysis tools use the conservative assumption that all neighbors of a net can switch simultaneously, thereby producing worst-case on net. However, logic correlations in circuit, this may not be realizable, resulting so-called false failure. Since problem has been shown NP-hard general, exact solutions possible. In paper, we therefore propose new heuristic eliminate...

High-performance digital circuits are facing increasingly severe signal integrity problems due to crosstalk noise and therefore the state-of-the-art static timing analysis (STA) methods consider crosstalk-induced delay variation. Current noise-aware STA compute noise-induced uncertainty for each net independently annotate appropriate changes of nets onto data paths associated clock determine violations. Since in individual contribute cumulatively paths, even small amounts pessimism...

We developed a ground observation system for solid precipitation using two-dimensional video disdrometer (2DVD). Among 16,010 particles observed by the system, around 10% of them were randomly sampled and manually classified into five classes which are snowflake, snowflake-like, intermediate, graupel-like, graupel. At first, each particle was represented as vector 72 features containing fractal dimension box-count to represent complexity shape. Feature analysis on dataset clarified...

Placement is one of the most difficult stages reconfigurable system-on-chip design flow.Designing highspeed systems requires efficient timing-driven placement algorithms.In this article we present a new algorithm based on simulated annealing method for island-style RSoC.Since RSoC hierarchical, our divided in two stages: global and detailed.At stage place groups logic elements (GLE) with respect to assigned input/output cells macroblocks.At detailed inside each GLE.We developed cost function...

β-turn is one of the most important reverse turns because its role in protein folding. Many computational methods have been studied for predicting β-turns and types. However, due to imbalanced dataset, performance still inadequate. In this study, we proposed a novel over-sampling technique FOST deal with class-imbalance problem. Experimental results on three standard benchmark datasets showed that our method comparable state-of-the-art methods. addition, applied algorithm five from UCI...

Cross-coupled noise analysis has become a critical concern in today's VLSI designs. Typically, makes the assumption that all aggressing nets can simultaneously switch same direction. This creates worst- case pulse on victim net often leads to false violations. In this article we present new approach uses logic implications identify maximum set of aggressor inject under constraints circuit. We propose an efficiently generate from transistor-level description and propagate them circuit using...

Progress in semiconductor process technology has made SOI transistors one of the most promising candidates for high performance and low power designs. With smaller diffusion capacitances, switch significantly faster than their traditional bulk MOS counterparts consume less per switching. However, design simulation circuits is more challenging due to complex behavior an transistor involving floating body effects, delay dependence on history switching, bipolar effect others. This paper devoted...

Progress in semiconductor process technology has made SOI transistors one of the most promising candidates for high performance and low power designs. With smaller diffusion capacitances, switch significantly faster than their traditional bulk MOS counterparts consume less per switching. However, design simulation circuits is more challenging due to complex behavior an transistor involving floating body effects, delay dependence on history switching, bipolar effect others. This paper devoted...

Sharing the methods of logical and physical synthesis can be an effective solution nanoelectronic circuits design problem. The resynthesis has a significant effect on subsequent efficiency. To solve this problem, models inter-gate at transistor level were developed earlier IPPM RAS. Proposed was adopted for structural optimization based information about implementation FinFET circuits. An algorithm developed. A new layout description model SP graph extension proposed. In case, degrees...

Reconfigurable system-on-chip (RSoC) is a device that contains configurable logic blocks and hard IP cores in the single chip. Designing high-speed digital circuits RSoC requires efficient timing-driven placement algorithms. In this article we present new algorithm based on simulated annealing method for island-style reconfigurable system-on-chip. We developed novel cost function half-perimeter wire length delay model. Lookup matrices both global local interconnections are used to accurately...

The paper is devoted to research and development of custom IP-blocks design methods in the form standard elements with regular layout structure layers polysilicon diffusion. For today leading developers microelectronic devices continue work out key modules systems, such as core microprocessors, microcontrollers completely custom-made a mode which final composition library not known beforehand, extremely low at transistor level. However, automation logic synthesis process for difficult due...

Timing margining is a key component of timing sign-off. Insufficient margin can lead to silicon failure and excessive pessimistic will entail unnecessary design optimization effort. intended cover the uncertainty in clock arrival times skews arising from within-die process variations. In highly scaled technologies, increased variations tend enforce an overestimation margins making it difficult for designs achieve target performance. this paper, we present more efficient methodology account...