Christoforos Kachris

ORCID: 0000-0003-0818-1902
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About
Contact & Profiles
Research Areas
  • Parallel Computing and Optimization Techniques
  • Interconnection Networks and Systems
  • Advanced Optical Network Technologies
  • Optical Network Technologies
  • Cloud Computing and Resource Management
  • Embedded Systems Design Techniques
  • Advanced Data Storage Technologies
  • Software-Defined Networks and 5G
  • Advanced Photonic Communication Systems
  • Advanced Memory and Neural Computing
  • Error Correcting Code Techniques
  • Network Packet Processing and Optimization
  • Advanced Wireless Communication Techniques
  • Advanced Neural Network Applications
  • VLSI and Analog Circuit Testing
  • Numerical Methods and Algorithms
  • Radiation Effects in Electronics
  • Semiconductor Lasers and Optical Devices
  • CCD and CMOS Imaging Sensors
  • Distributed systems and fault tolerance
  • Distributed and Parallel Computing Systems
  • Low-power high-performance VLSI design
  • Neural Networks and Reservoir Computing
  • Topic Modeling
  • Anomaly Detection Techniques and Applications

University of West Attica
2024-2025

National Technical University of Athens
2016-2022

Institute of Communication and Computer Systems
2016-2022

Democritus University of Thrace
2012-2021

Athens Information Technology
2011-2015

Queen's University
2014

Foundation for Research and Technology Hellas
2010-2012

FORTH Institute of Electronic Structure and Laser
2010

Hella (Germany)
2010

Delft University of Technology
2006-2008

Data centers are experiencing an exponential increase in the amount of network traffic that they have to sustain due cloud computing and several emerging web applications. To face this load, large data required with thousands servers interconnected high bandwidth switches. Current center networks, based on electronic packet switches, consume excessive power handle increased communication Optical interconnects gained attention recently as a promising solution offering throughput, low latency...

10.1109/surv.2011.122111.00069 article EN IEEE Communications Surveys & Tutorials 2012-01-01

Warehouse-scale data center operators need much-higher-bandwidth intra-data networks (DCNs) to sustain the increase of network traffic due cloud computing and other emerging web applications. Current DCNs based on commodity switches require excessive amounts power face this increase. Optical intra-DCN interconnection have recently emerged as a promising solution that can provide higher throughput while consuming less power. This article provides an update recent developments in field...

10.1109/mcom.2013.6588648 article EN IEEE Communications Magazine 2013-09-01

Large language models (LLMs) have emerged as powerful tools for natural processing tasks, revolutionizing the field with their ability to understand and generate human-like text. As demand more sophisticated LLMs continues grow, there is a pressing need address computational challenges associated scale complexity. This paper presents comprehensive survey of hardware accelerators designed enhance performance energy efficiency large models. By examining diverse range accelerators, including...

10.3390/app15020586 article EN cc-by Applied Sciences 2025-01-09

Due to the rapid increase in network traffic last few years, many telecommunication operators have started transitions 100-Gb/s optical networks and beyond. However, high-speed need more efficient forward error correction (FEC) codes deal with impairments, such as uncompensated chromatic dispersion, polarization mode nonlinear effects, keep bit rate (BER) at long distances sufficiently low. To address these issues, new FEC codes, called third-generation been proposed. A majority of are based...

10.1109/comst.2014.2361754 article EN IEEE Communications Surveys & Tutorials 2014-10-08

Data centers are experiencing an exponential increase in the amount of network traffic that they have to sustain due cloud computing and several emerging web applications.To face this load, large data required with thousands servers interconnected high bandwidth switches.Current center, based on general purpose processor, consume excessive power while their utilization is quite low.Hardware accelerators can provide energy efficiency for many applications but lack programming processors.In...

10.1109/fpl.2016.7577381 article EN 2016-08-01

Data center networks are facing growing challenges to deliver higher bandwidth efficiency, lower latency, better flexibility, and cost. Various optical interconnect schemes have been proposed take advantage of the high capacity low power consumption offered by switching. However, these cannot offer flexible sharing due large granularity in circuit switching, they require costly components. In this paper, we introduce a novel data network architecture based on cyclic arrayed waveguide grating...

10.1109/jstqe.2012.2209409 article EN IEEE Journal of Selected Topics in Quantum Electronics 2012-07-19

Large Language Models (LLMs) have emerged as powerful tools for natural language processing tasks, revolutionizing the field with their ability to understand and generate human-like text. As demand more sophisticated LLMs continues grow, there is a pressing need address computational challenges associated scale complexity. This paper presents comprehensive survey on hardware accelerators designed enhance performance energy efficiency of Models. By examining diverse range accelerators,...

10.48550/arxiv.2401.09890 preprint EN cc-by arXiv (Cornell University) 2024-01-01

The aim of cognition in optical networks is to introduce intelligence into the control plane that allows for autonomous end-to-end performance optimization and minimization required human intervention, particularly targeted at heterogeneous network scenarios. A cognitive observes, learns, makes informed decisions based on its current status knowledge about past their results. To test operation algorithms real time, we created first operational testbed a Cognitive Heterogeneous Reconfigurable...

10.1364/jocn.7.00a344 article EN Journal of Optical Communications and Networking 2015-01-12

Network Function Virtualization (NFV) refers to the use of commodity hardware resources as basic platform perform specialized network functions opposed devices. Currently, NFV is mainly implemented based on general purpose processors, or processors. In this paper we propose FPGAs an ideal for that can be used provide both flexibility virtualizations and high performance hardware. We present early attempts using dynamic reconfiguration in processing applications flexible opportunities...

10.48550/arxiv.1406.0309 preprint EN other-oa arXiv (Cornell University) 2014-01-01

The advent of high-performance computing (HPC) in recent years has led to its increasing use brain studies through computational models. scale and complexity such models are constantly increasing, leading challenging requirements. Even though modern HPC platforms can often deal with challenges, the vast diversity modeling field does not permit for a homogeneous acceleration platform effectively address complete array requirements.In this paper we propose build BrainFrame, heterogeneous that...

10.1088/1741-2552/aa7fc5 article EN cc-by Journal of Neural Engineering 2017-07-14

Optical interconnection networks have appeared as a promising technology that can be used to face the increase of network traffic in data centres. Data centre based on optical switches provide lower latency, higher throughput and reduced power consumption. Currently, there are several approaches been studied but is still no commercial implementation. This paper presents roadmap demand next years utilization future

10.1109/icton.2015.7193535 article EN 2015-07-01

FPGA-based accelerators are becoming first class citizens in data centers. Adding FPGAs centers can lead to higher compute densities with improved energy efficiency for latency critical workloads, such as financial applications. However FPGA deployment datacenters brings difficulties both application developers, and cloud providers. Application writers need deal the interfacing of on top logic/algorithms. On other hand, providers reluctant face risk that their hardware remains underutilized,...

10.23919/fpl.2017.8056788 article EN 2017-09-01

Naive Bayes is one of the most effective and efficient classification algorithms its classifiers still tend to perform very well under unrealistic assumptions. Especially for small sample sizes, naive can outperform more powerful classifiers. Therefore acceleration such an algorithm becomes a great asset in machine learning applications. The SDSoC environment provides framework developing delivering hardware accelerated embedded processor applications using standard programming languages. A...

10.1109/mocast.2019.8741875 article EN 2019-05-01

10.1016/j.suscom.2021.100520 article EN Sustainable Computing Informatics and Systems 2021-02-03

This paper presents two bandwidth assignments algorithms for an optical OFDM-based data center network. The proposed scheme can provide up to 95% utilization and 14% lower power consumption compared a WDM-based

10.1364/nfoec.2012.jth2a.34 article EN 2012-01-01

Caffe is a deep learning framework, originally developed at UC Berkeley and widely used in large-scale industrial applications such as vision, speech, multimedia. It supports many different types of architectures CNNs (convolutional neural networks) geared towards image classification recognition. In this paper we develop platform for the efficient deployment acceleration framework on embedded systems that are based Zynq SoC. The most computational intensive part processing convolution...

10.1109/mocast.2018.8376580 article EN 2018-05-01

Manipulating big-data entries of emerging server workloads requires a design paradigm shift towards more aggressive system-level architecture solutions. From software perspective, the MapReduce framework is prominent parallel data processing tool as volume to analyze grows rapidly. FPGAs can be used accelerate and reduce significantly power consumption. However, have not been deployed in centers due high programming complexity hardware. In this paper we present HLSMapReduceFlow, i.e. novel...

10.1109/samos.2015.7363656 article EN 2015-07-01

Large Language Models (LLMs) have emerged as powerful tools for natural language processing tasks, revolutionizing the field with their ability to understand and generate human-like text. In this paper, we present a comprehensive survey of several research efforts that been presented acceleration transformer networks using hardware accelerators. The presents frameworks proposed then performs qualitative quantitative comparison regarding technology, platform (FPGA, ASIC, In-Memory, GPU),...

10.48550/arxiv.2409.03384 preprint EN arXiv (Cornell University) 2024-09-05

This paper presents a study on the energy efficiency of adaptive optical OFDM in data center's networks. The DSP architecture proposed scheme is targeted to an FPGA and achieves more than 70% lower consumption compared conventional modulation.

10.1364/nfoec.2011.jwa087 article EN 2011-01-01

Low Density Parity Check(LDPC) codes are a special class of error correction widely used in communication and disk storage systems, due to their Shannon limit approaching performance favorable structure. In this paper, methodology for optimized hardware multiplication by constant matrices GF(2) is introduced then applied the Quasi-Cyclic LDPC encoding algorithm. Taking advantage fact that parity check matrix rarely changes, signals many cases hard-wired into LUTs thus cyclic-shifters...

10.1109/fpl.2013.6645587 article EN 2013-09-01
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