In this paper, a 4th-order low-pass continuous-time analog filter is presented, that implemented with the cascade of two efficient and compact biquadratic cells, realized using Super-Source-Follower topology. The cell uses only capacitors four transistors: transistors for signal processing as current sources biasing purpose. prototype has been integrated in 0.18 μm CMOS technology. For 33 MHz cut-off frequency, performs 18 dBm-IIP3 tones at 2 3 MHz, total 770 μA from single 1.8 V supply voltage.

A 0.55 V supply voltage fourth-order low-pass continuous-time filter is presented. The low-voltage operating point achieved by an improved bias circuit that uses different opamp input and output common-mode voltages. architecture composed two active- G <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> -RC biquadratic cells, which use a single per-cell with unity-gain-bandwidth comparable to the cut-off frequency. - 3 dB frequency 12 MHz...

A 90 nm-CMOS power-optimized analog baseband chain for ultra-low-power impulse-radio ultra-wideband (IR-UWB) receivers is presented. The proposed device merges the functions of a programmable gain amplifier (PGA) and low-pass filter (LPF). It consists cascade three biquadratic cells made up by opamps in series-shunt configuration, which features high input impedance, low load effects blocks, better frequency response. opamp parameters are included overall biquad transfer function. This...

The CLARO-CMOS is an application specific integrated circuit (ASIC) designed for fast photon counting with pixellated photodetectors such as multi-anode photomultiplier tubes (Ma-PMT), micro-channel plates (MCP), and silicon photomultipliers (SiPM). first prototype has four channels, each a charge sensitive amplifier settable gain discriminator threshold, providing hit information channel independently. design was realized in long-established, stable inexpensive 0.35 μm CMOS technology,...

The source follower is a well known basic building block for CMOS design. A capacitively loaded acts as 1 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">st</sup> -order low- pass filter and exhibits excellent linearity, especially with reduced overdrive voltages. In these source-follower features have been used advantageously in the design of 2 xmlns:xlink="http://www.w3.org/1999/xlink">nd</sup> (biquadratic) low-pass 4...

Power consumption of high-speed low-resolution analog-to-digital converters (ADCs) can be reduced by means calibration. However, this solution has some drawbacks such as time slot allocation for calibration and die area increase. This paper presents a 5-bit 1-Gs/s ADC without calibration, fabricated in 90-nm CMOS. Low power been ensured operating at both architecture comparator levels. A folded interpolated adopted. compared to standard solutions that use static preamplifiers, the...

This brief presents a novel biquadratic cell (biquad) based on the flipped-source-follower (FSF) circuit. The main idea is to exploit FSF circuit as basic building block for low-pass second-order filter, taking advantage of its well-known strengths, like low-output impedance, low-noise, large in-band linearity, and low power. Thanks very essential circuit, resulting biquad power-efficient broad bandwidth stage, with low-noise performance. In order validate design idea, extensive circuital...

Clinical ions beams for cancer treatment provide maximum energy deposition (Bragg peak (BP)) at the end of their range and practically no dose behind. This enables a more efficient therapeutic option comparing with classical photon-based radiotherapy where is deposited body interface. Obviously, minimum-error BP detection is, thus, key aspect this treatment. paper investigates promising technique, based on so-called ionoacoustic effect. The causes small (millikelvin) heating surrounding...

In this paper, a fourth-order continuous-time follow-the-leader-feedback (FLFB) low-pass (LP) filter is presented. The outstanding FLFB noise behavior exploited to minimize power consumption. This achieved by means of customized implementation solutions based on combination Active- <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">RC</i> /Active- <inline-formula xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$g_{m}$...

An analog baseband chain for a multistandard (Bluetooth, WCDMA/UMTS, and WLAN) reconfigurable receiver in 0.13 mum CMOS occupying 1.65 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> is presented. The circuit consists of an open-loop programmable-gain amplifier (PGA1), active-G <sub xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> -RC low-pass filter (LPF), closed-loop (PGA2). gain can be programmed the range -6 divide 68 dB, while...

A 90nm, IR UWB, duty-cycled transceiver chipset, for operation from 7 to 9.8GHz and compliant the IEEE802.15.4a upcoming IEEE802.15.6 standard, is presented. The complete, transmitter provides +1dBm peak output power, consuming 4.4mW. receiver front-end shows -88dBm sensitivity at 0.85Mbps a digital synchronization algorithm enables real-time duty cycling, resulting in mean power consumption of 3mW.

This brief presents a 4 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sup> -order continuous-time analog filter based on Flipped-Source-Follower stage. Source-Follower (SF) filters typically adopt pseudo-differential topology (critical for matching and bulk/substrate noise rejection) are realized in not recent CMOS processes (130nm or 180nm) due to the intrinsic voltage headroom required by SF operation. The proposed device solves above...

This paper presents the design and experimental characterization of a Proton Sound Detector (ProSD), device that physically captures senses weak acoustic signal emitted by fast energy deposition at end same proton beam range. The measured Time-of-Flight provides very accurate (13 μm accuracy) measure penetration depth in water, improving range verification accuracy w.r.t. previous works pre-clinical scenarios. suggests interesting possibilities for high-accuracy real-time monitoring...

A fast charge sensitive preamplifier was designed and built in a 90 nm CMOS technology. The work is part of the R&D effort towards read out pixel or small strip sensors next generation HEP experiments. features outstanding noise performance given its wide bandwidth, with ENC (equivalent charge) about 350 electrons RMS detector 1 pF capacitance. With proper filtering, drops to less than 200 RMS. Power consumption 5 mW for one channel, closed loop bandwith 180 MHz, risetime down 2 ns fastest...

A radiation-hard BGR (bandgap voltage reference) circuit is here presented. It's able to maintain the output accuracy over process, voltage, and temperature (PVT) variations, combined with extremely high total-ionizing-dose (up 800 Mrad (SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> )), as required by next experiments upgrades of Large Hadron Collider (LHC). The design has been dealt starting from several experimental results,...

In this paper an overview on the main issues in analog IC design scaled CMOS technology is presented. Decreasing length of MOS channel and gate oxide has led to undoubted advantages terms chip area, speed power consumption (mainly exploited digital parts). Besides, some drawbacks are introduced term leakage reliability. Moreover, lower supply voltage requirement designers find new circuital solution guarantee required performance.

An eight-channel readout front end for Large Hadron Collider (LHC) ATLAS muon-drift-tubes detectors is hereby presented (defined 8 × AFE). The system composed by the cascade of analog signal processing and Wilkinson A/D, performing both time-over-threshold charge measurement. sensitivity at output chain 14 mV/fC, while equivalent-noisecharge 0.6 fC (~3.38 ke), <;12-ns preamplifier rise time. These performances have been achieved managing very high detector parasitic capacitance front-end...

The wireless networks popularity rapidly requires a significant effort on low-power low-cost, and highly integrated RF ICs, where the power consumption reduction of transceiver each block becomes fundamental importance. Analog base-band continuous-time filters embedded in receiver path are here addressed with three examples. first example is an active-G <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> 7-RC filter which uses opamp...

A low-power high-linearity variable-gain-amplifier, VGA, in a 0.13 mum CMOS technology to be embedded multi-standard receiver (WLAN, UMTS, GSM, and Bluetooth) is reported. This architecture presents considerable different VGA requirements (in terms of bandwidth, DC-gain, common mode input voltage) for the four telecom standards processed. Thus proposed addition power control, demanded accommodate feed one channel filter. The prototype features gain levels from -10dB 36dB, with 25dBm IIP3 an...

<?Pub Dtl=""?> The upgrade of the Pierre Auger Observatory required a larger number detectors that implies dramatic increase power consumption. As analog-to-digital converter (ADC) is most critical circuit block, an integrated solution here proposed. A 10 b 50-MSps 5-stage pipeline ADC implemented in 65 nm digital CMOS. It achieves 50.3 dB signal-to-noise and distortion ratio (SNDR), 52.3 (SNR), 59.2 spurious free dynamic range (SFDR) for full-scale input sinewave at Nyquist frequency....

This paper presents a multidisciplinary experiment where population of neurons, dissociated from rat hippocampi, has been cultivated over CMOS-based micro-electrode array (MEA) and its electrical activity detected mapped by an advanced spike-sorting algorithm implemented on FPGA. MEAs are characterized low signal-to-noise ratios caused both the contactless sensing weak extracellular voltages high noise power coming cells analog electronics signal processing. SNR forces to utilize rejection...

Proton sound detectors rely on sensing the weak thermoacoustic signals emitted by fast energy deposition at end of beam penetration path through absorber. The ions/protons is first converted into heat, and then, pressure a thermodynamic process. signal propagates absorber, it read an acoustic sensor, which, in turn, converts wave analog electrical voltage. Such digitalized front-end. Its digital representation used for measurement depth. This emerging technique attracts attention both...

This paper presents the results of a multidisciplinary experiment where electrical activity rat hippocampus cultured neurons population has been detected and mapped by an advanced FPGA spike-sorting algorithm. Neurons are growth over silicon chip that is thus capacitively coupled with neuronal cells. Due to noise power coming from bio-silicon interface analog electronics signal processing, Action Potentials detection intrinsically needs rejection algorithms which often software/off-line...

In this brief, a 28.8-MHz -3-dB frequency low-pass analog filter is presented. The synthesizes fourth-order Butterworth transfer function, exploiting the well-known Sallen-Key (SK) biquadratic cell. out-of-band zeros typically present in SK implementations are hereby completely canceled by using low-power auxiliary path. This leads to significant improvement of stop-band rejection, at cost small power for same path biasing. design exhibits very large in-band IIP3 over entire bandwidth (20...