The chromatic index $\chi'(G)$ of a graph $G$ is the smallest $k$ for which admits an edge $k$-coloring such that any two adjacent edges have distinct colors. strong $\chi'_s(G)$ has with condition at distance most 2 receive A 1-planar if it can be drawn in plane so each crossed by one other edge. In this paper, we show every maximum average degree $\bar{d}(G)$ $\chi'_{s}(G)\le (2\bar{d}(G)-1)\chi'(G)$. As corollary, prove $\Delta$ $\chi'_{\rm s}(G)\le 14\Delta$, improves result, due to...

This paper presents a new operation (exorlink) and an algorithm to minimize Exclusive-OR Sum-of-Products expressions (ESOPs) for multiple valued input, two output, incompletely specified functions. Exorlink is more powerful than any other existing one this problem. Evaluation on benchmark functions given it proves the superiority of program those known from literature.

The prices of different quality river crabs on the market can vary several times. Therefore, internal identification and accurate sorting are particularly important for improving economic benefits industry. Using existing methods by labor weight to meet urgent needs mechanization intelligence in crab breeding industry is difficult. this paper proposes an improved BP neural network model based a genetic algorithm, which grade quality. We comprehensively considered four characteristics as...

Article Free Access Share on A comprehensive approach to logic synthesis and physical design for two-dimensional arrays Authors: Andisheh Sarabi Portland State University, Department of Electrical Engineering, P.O. Box 751, Portland, OR ORView Profile , Ning Song Malgorzata Chrzanowska-Jeske Marek A. Perkowski Authors Info & Claims DAC '94: Proceedings the 31st annual Design Automation ConferenceJune 1994 Pages 321–326https://doi.org/10.1145/196244.196398Published:06 June 1994Publication...

A cube operation, EXORLINK, and its application to the minimization of multiple-valued input, multi-output exclusive sums products (ESOPs) for incompletely specified Boolean functions, are presented. EXORLINK generalizes all operations, such as crosslink, unlink, X-merge. The authors' program, EXORCISM-MV-2, gives efficient results functions that have an arbitrary number values each input variables. This allows realization a wider class circuits implement ESOP expressions. Evaluation on...

The paper proposes a new layout-driven multi-level logic factorization methodology for regular arrays of two-input cells, that can find practical applications in fine-grain FPGA design, standard cell, gate matrix layout and sub-micron technologies. A algorithm AND/OR/EXOR with multi-valued literals is introduced, has application to minimization Logic Cell Arrays, improves on previous results. It shown an extended cube representation efficient rules be used, generalize the ESOP approach....

We derive necessary and sufficient conditions which guarantee that a multiplying set of monomials generates exactly Sylvester A-resultant for three bivariate polynomials with given planar Newton polygon. show valid sets come in complementary pairs, any two pairs can be used to index the rows columns pure Bezoutian same polygon.The include Diophantine equations solved generate therefore corresponding $A$-resultants. Examples relevant Geometric Modeling are provided, including new family...

This paper introduces a new design approach that combines stages of logic and physical design. The function is synthesized mapped to two‐dimensional array cells. generalizes PLAs, XPLAs cellular Maitra cascades. Each cell can be programmed wire, an inverter, or two‐input AND, OR EXOR gate (with any subset inputs negated). take output four neighbor cells buses as its inputs, sends result back them. geometrical model well suited for both fine‐grain FPGA realization sea‐of‐gates custom ASIC...

The characteristic feature of the new cellular-architecture FPGA is a local connectivity between adjacent cells. This paper presents nontraditional approaches to layout synthesis FPGA. In first approach, multi-level network, in form DAG, mapped target architecture using simulated evolution. parameters controlling evolution are defined such that routing structure considered during placement. second restricted multilevel network (RML), obtained by driven factorization two-level representation...

The proposed factorization methods for regular arrays of two-input cells have several important advantages over the existing logic representations and methodologies. (1) representation design implementation are consistent. (2) stages synthesis physical effectively merged into a single stage. (3) structure mapping solution is rectangle. (4) Since connections mainly between neighboring cells, wire delay reduced compared to other methods. (5) regular, creation high-performance tools...

A graph is called 1-planar if it can be drawn in the Euclidean plane <TEX>${\mathbb{R}}^2$</TEX> such that each edge crossed by at most one other edge. The weight of an sum degrees two ends. It known every planar minimum degree <TEX>${\delta}{\geq}3$</TEX> has with 13. In present paper, we show existence edges 25 3-connected graphs.

The work described in this paper is a component of our comprehensive approach to the low-level synthesis (logic and layout synthesis) Cellular-Architecture (CA-type) FPGAs. A multiple-output logic function represented as collection complex terms. Each term assigned separate row CA-type FPGA. These terms are collected using EXOR or OR gates create outputs, initially one output per column. In an algorithm for multiple column folding FPGAs presented. formulation problem similar gate matrix but...

Stochastic machine minimization problems are motivated by resource allocation issues in communication networks and image formation systems. We consider the following stochastic problem: Initially (at time t=0) there N projects (jobs, messages) available for processing. New arrive according to a Poisson process with fate /spl mu/. All projects' processing times independent samples of an exponentially distributed random variable T. There is unlimited number identical machines projects. A timer...